16 Oct, 2007
9 commits
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This driver was using hooks that were very recently removed.
Signed-off-by: Jeff Garzik
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Signed-off-by: Kristoffer Ericson
Signed-off-by: Jeff Garzik -
The strn_pattern_cmp routine does not handle a blank name parameter
properly. The only patterns which should match a blank name are "*"
and an explicit "". If the function is passed a blank name in current
code, it will always match against the patt parameter. The bug manifests
itself as the device with the empty model name always matching the first
device in the DMA blacklist, forcing it to revert to PIO mode.Signed-off-by: Andrew Paprocki
Signed-off-by: Jeff Garzik -
This patch adds a port map for ICH9 and ICH8 SATA controllers that have only 2 ports available in that mode.
Signed-off-by: Jason Gaston
Signed-off-by: Jeff Garzik -
This is a driver for the ATA controller on the Geode CS5536 companion
chip. The PCI device ID for this device was previously claimed by
pata_amd.c but the PIO timings were not correct. This driver also
works around a bug in some BIOSes that handle unaligned access to the
PCI config registers poorly. Finally, the driver allows fallback to
using MSR registers for configuration on BIOSes that are truly
broken.Signed-off-by: Martin K. Petersen
Signed-off-by: Jeff Garzik -
ST9160821AS / 3.CCD does spurious completions too. Blacklist it.
Signed-off-by: Tejun Heo
Signed-off-by: Jeff Garzik -
After commands which can change device configuration, EH is scheduled
to revalidate and reconfigure the device. Host link was incorrectly
used unconditionally when scheduling EH action. This resulted in
bogus revalidation request and mismatched configuration between device
and driver. Fix it.This bug was reported by Igor Durdanovic.
Signed-off-by: Tejun Heo
Cc: Igor Durdanovic
Signed-off-by: Jeff Garzik -
Add the Software NCQ support to sata_nv.c for MCP51/MCP55/MCP61 SATA
controller. NCQ function is disable by default, you can enable it
with 'swncq=1'. NCQ will be turned off if the drive is Maxtor on
MCP51 or MCP55 rev 0xa2 platform.[akpm@linux-foundation.org: build fix]
Signed-off-by: Kuan Luo
Signed-off-by: Peer Chen
Cc: Zoltan Boszormenyi
Signed-off-by: Andrew Morton
Signed-off-by: Jeff Garzik -
This patch adds MMIO support to the pata_sil680 for taskfile IOs,
based on what the old siimage does.I haven't bothered changing the chip setup stuff from PCI config
cycles to MMIO though (siimage does it), I don't think it matters,
I've only adapted it to use MMIO for taskfile accesses.I've tested it on a Cell blade and it seems to work fine.
Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: Jeff Garzik
15 Oct, 2007
1 commit
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Signed-off-by: Al Viro
Signed-off-by: Linus Torvalds
14 Oct, 2007
1 commit
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Trivial unused variable fix
Signed-off-by: Grant Likely
Signed-off-by: Linus Torvalds
13 Oct, 2007
29 commits
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* remove pointless pci_dev_to_dev() wrapper. Just directly reference
the embedded struct device like everyone else does.* pata_cs5520: delete cs5520_remove_one(), it was a duplicate of
ata_pci_remove_one()* linux/libata.h: don't bother including linux/pci.h, we don't need it.
Simply declare 'struct pci_dev' and assume interested parties will
include the header, as they should be doing anyway.* linux/libata.h: consolidate all CONFIG_PCI declarations into a
single location in the header.Signed-off-by: Jeff Garzik
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PMP registers used to be accessed with dedicated accessors ->pmp_read
and ->pmp_write. During reset, those callbacks are called with the
port frozen so they should be able to run without depending on
interrupt delivery. To achieve this, they were implemented polling.However, as resetting the host port makes the PMP to isolate fan-out
ports until SError.X is cleared, resetting fan-out ports while port is
frozen doesn't buy much additional safety.This patch updates libata PMP support such that PMP registers are
accessed using regular ata_exec_internal() mechanism and kills
->pmp_read/write() callbacks. The following changes are made.* PMP access helpers - sata_pmp_read_init_tf(), sata_pmp_read_val(),
sata_pmp_write_init_tf() are folded into sata_pmp_read/write() which
are now standalone PMP register access functions.* sata_pmp_read/write() returns err_mask instead of rc. This is
consistent with other functions which issue internal commands and
allows more detailed error reporting.* ahci interrupt handler is modified to ignore BAD_PMP and
spurious/illegal completion IRQs while reset is in progress. These
conditions are expected during reset.Signed-off-by: Tejun Heo
Signed-off-by: Jeff Garzik -
Implement ATA_PFLAG_RESETTING. This flag is set while reset is in
progress. It's set before prereset is called and cleared after reset
fails or postreset is finished.This flag itself doesn't have any function. It will be used by LLDs
to tell whether reset is in progress if it needs to behave differently
during reset.Signed-off-by: Tejun Heo
Signed-off-by: Jeff Garzik -
Add @timeout argument to ata_exec_internal[_sg](). If 0, default
timeout ata_probe_timeout is used.Signed-off-by: Tejun Heo
Signed-off-by: Jeff Garzik -
Asynchronous notification on ICH9 didn't work because it didn't write
AN FIS into the RX area - it only updates SNotification. Also,
snooping SDB_FIS RX area is racy against further SDB FIS receptions.
Let sata_async_notification() determine using SNTF if it's available
and snoop RX area iff SNTF isn't availableSigned-off-by: Tejun Heo
Cc: Kristen Carlson Accardi
Signed-off-by: Jeff Garzik -
Now that we have pp->intr_mask, move PORT_IRQ_BAD_PMP enabling to
ahci_pmp_attach/detach() where it belongs.Signed-off-by: Tejun Heo
Signed-off-by: Jeff Garzik -
ahci had problems with NCQ over PMP and NCQ used to be disabled while
PMP was attached. After fixing the problem, the temporary NCQ
disabling code wasn't removed completely. Kill the remaining piece.Signed-off-by: Tejun Heo
Signed-off-by: Jeff Garzik -
Tasks in uninterruptible sleep might be woken up by unrelated events
and should check whether the condition it was waiting for has actually
triggered. Wrap schedule_timeout_uninterruptible() in loop to achieve
it.Signed-off-by: Tejun Heo
Signed-off-by: Jeff Garzik -
ATA_EHI_NO_AUTOPSY and ATA_EHI_QUIET are used during initial probing
to skip exception analysis and reporting. Usually, there's nothing to
report but on some allowed but rare corner cases (e.g. phy status
changed interrupt when IRQ is enabled on frozen port - this happens if
IRQ pending status isn't cleared in the IRQ router or controller)
exception messages get printed.Skip reporting if ATA_EHI_QUIET is set.
Signed-off-by: Tejun Heo
Signed-off-by: Jeff Garzik -
ehi description field is used to carry LLD specific controller
description. Sometimes, it's used without clearing before and LLD
description gets printed with exception information one more time.
Clear after printing.Signed-off-by: Tejun Heo
Signed-off-by: Jeff Garzik -
PATA part of all current JMB controllers behave the same way and
JMicron confirms that all future ones will stay compatible. Drop
device matching and match only vendor and class.Signed-off-by: Tejun Heo
Cc: Ethan Hsiao
Cc: Justin Tsai
Signed-off-by: Jeff Garzik -
ST9160821AS / 3.ALD also does spurious NCQ completions. Disable NCQ.
Signed-off-by: Tejun Heo
Signed-off-by: Jeff Garzik -
On a cable there may be
eighty wires or perhaps forty
and we learn about its type
In the world of ACPISo we call the GTM
And we find the the timing rate
And we look through it to see
If eighty wire it must beTiming lives in ACPI routines
ACPI routines, ACPI routines
Timing lives in ACPI routines
ACPI routes ACPI routinesAnd the drivers last you see
Picking up unknown pci ids
and the code begins to workTiming lives in ACPI routines
ACPI routines, ACPI routines
Timing lives in ACPI routines
ACPI routes ACPI routines[Full speed ahead, Mr Hacker, full speed ahead]
Full speed over here sir!
Checking Cable, checking cable
Aye aye, 80 wire,
Heaven heaven]If we use ACPI (ACPI)
Every box (every box) has all we need (has all we need)
Cable type (cable type) and mode timing (mode timing)
In our ATA (in our ATA) subroutines (subroutines, ha ha)Timing lives in ACPI routines
ACPI routines, ACPI routines
Timing lives in ACPI routines
ACPI routes ACPI routines
Timing lives in ACPI routines
ACPI routines, ACPI routines
Timing lives in ACPI routines
ACPI routes ACPI routinesSigned-off-by: Alan Cox
Signed-off-by: Jeff Garzik -
Talk to the dark side our driver has to, yes. Much misleading is the
data. Store it in a structure we do so that it may be parsed.Signed-off-by: Alan Cox
--
Whats small, old and shouts phrases out of order across mountains ?
Yodla..
Signed-off-by: Jeff Garzik -
HDT722516DLA380 does spurious completion of NCQ commands. Blacklist
it.Signed-off-by: Tejun Heo
Cc: Frans Pop
Signed-off-by: Jeff Garzik -
Seagate Barracuda ST380817AS has troubles with NCQ. For example,
unpacking a tarball on an XFS filesystem gives this:ata1.00: exception Emask 0x0 SAct 0x1 SErr 0x0 action 0x2 frozen
ata1.00: cmd 61/40:00:29:a3:98/00:00:00:00:00/40 tag 0 cdb 0x0 data 32768 out
res 40/00:00:00:00:00/00:00:00:00:00/00 Emask 0x4 (timeout)More info here:
http://lkml.org/lkml/2007/1/21/76Blacklist it!
Signed-off-by: Paolo Ornati
Signed-off-by: Tejun Heo
Signed-off-by: Jeff Garzik -
Let's see what explodes.
Signed-off-by: Jeff Garzik
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Some controller variants snoop the ATAPI length value for Packet
transfers to do state machine and FIFO management. Thus we want to
set it properly, even for cases where it is otherwise meaningless.Signed-off-by: Alan Cox
Signed-off-by: Andrew Morton
Signed-off-by: Jeff Garzik -
Correct handling of SRST reset sequences. After an SRST it is undefined
whether the drive has gone back to PIO0. In order to talk safely we should
talk slowly and carefully until we know.Thus when we do the reset if the controller has a pio setup method we call it
to flip back to PIO 0 and a known state. After the reset completes the
identify will then be done at the safe speed and the drive/controller will
pick suitable faster modes and reconfigure the controller to these timings.As a side effect it means we force the controller to PIO 0 as we bring it up
which fixes funnies on a few systems where the BIOS firmware leaves us in an
interesting choice of modes, or embedded boxes with no firmware which come up
in random states.For smart controllers there is nothing to do - they know about this
internally.Signed-off-by: Alan Cox
Signed-off-by: Andrew Morton
Signed-off-by: Jeff Garzik -
Modern laptops with hotswap bays still tend to utilise a PATA interface
on a SATA bridge, generally with the host controller in some legacy
emulation mode rather than AHCI. This means that the existing hotplug
code in libata is unable to work. The ACPI specification states that
these devices can send notifications when hotswapped, which avoids the
need to obtain notification from the controller. This patch uses the
existing libata-acpi code and simply registers a notification in order
to trigger a rescan whenever the firmware signals an event.Signed-off-by: Matthew Garrett
Signed-off-by: Jeff Garzik -
This is useful when debugging, handling problem systems, or for
distributions just to get the system installed so it can be sorted
out later.This is a bit smarter than the old IDE one and lets you do
libata.dma=0 Disable all PATA DMA like old IDE
libata.dma=1 Disk DMA only
libata.dma=2 ATAPI DMA only
libata.dma=4 CF DMA only(or combinations thereof - 0,1,3 being the useful ones I suspect)
(I've split CF as it seems to be a seperate case of pain and suffering
different to the others and caused by assorted PIO wired adapters etc)Signed-off-by: Alan Cox
[edited to work on SATA too, changing name from 'pata_dma' to 'dma']
Signed-off-by: Jeff Garzik -
Signed-off-by: Peer Chen
Signed-off-by: Jeff Garzik -
This adds human-readable decoding of the ATA status and error registers
(similar to what drivers/ide does) as well as the SATA Serror register
to libata error handling output. This prevents the need to pore
through standards documents to figure out the meaning of the bits
in these registers when looking at error reports. Some bits that
drivers/ide decoded are not decoded here, since the bits are either
command-dependent or obsolete, and properly parsing them would add
too much complexity.Signed-off-by: Robert Hancock
[edited slightly to make output a bit more symmetric]
Signed-off-by: Jeff Garzik -
Of course some controllers lie about PMP support. Black list them.
Signed-off-by: Tejun Heo
Signed-off-by: Jeff Garzik -
Private pi.flags area is full and we need more private flags. Move
host private flags over to pi.private_data. During initialization,
these flags are copied to hpriv->flags.Signed-off-by: Tejun Heo
Signed-off-by: Jeff Garzik -
Implement AHCI PMP support. ahci only supports command based
switching. Also, for some reason, NCQ over PMP doesn't work now.
Other than that, everything works.Tested on ICH9R, JMB360/363 + SIMG3726, 4726 and 5744.
Signed-off-by: Tejun Heo
Cc: Forrest Zhao
Signed-off-by: Jeff Garzik -
As DEV_RST (hardreset) sometimes fail to recover the controller
(especially after PMP DMA CS errata). In such cases, perform PORT_RST
prior to DEV_RST.Signed-off-by: Tejun Heo
Signed-off-by: Jeff Garzik -
Implement PMP support. sil24 supports full FIS-switching. However,
it has a PMP DMA CS errata which requires port-wide resetting if
commands are outstanding to three or more devices when an error occurs
on one of them.ATAPI commands often result in CHECK SENSE and it's crucial to not
reset them before fetching sense data. Unfortunately, ATAPI CHECK
SENSE causes a lot of problem if command is outstanding to any other
device usually resulting in port-wide reset. So, sata_sil24
implements sil24_qc_defer() which guarantees ATAPI command is run by
itself.Signed-off-by: Tejun Heo
Signed-off-by: Jeff Garzik -
Implement sata_pmp_qc_defer_cmd_switch() - standard qc_defer for
command switching PMP support.Signed-off-by: Tejun Heo
Signed-off-by: Jeff Garzik
