09 Jun, 2017
40 commits
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DDR50 tuning is optinally defined in sd 3.0 spec. Per IC guys
suggestion, it internally already uses a fixed optimized timing
and normally does not require tuning.Make it optionally and platform can claim SDHCI_DDR50_NEEDS_TUNING
support if it wants tuning.Signed-off-by: Dong Aisheng
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According to RM, Bit[11-8] is MUX_MODE which is configured by
the PIN_FUNC_ID automatically, specify it in config part is wrong
and violates the binding doc. So remove them all.It can also avoid the future confusing when customer wants to
configure a pad by following the exist code.Signed-off-by: Dong Aisheng
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Add i.MX7ULP binding doc. Note i.MX7ULP PIN_FUNC_ID consists of 4
integers as it shares one mux and config register as follows:Also fix the copyright.
Signed-off-by: Dong Aisheng
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'vin-supply' property used in ldo-bypass mode while 'vin-supply' deleted
in ldo-enable mode on v4.9 rather than dirctly switch 'supply' to internal
regulator and external pmic regulator on v4.1. Correct it for all *-ldo.dts,
otherwise, still work in ldo-bypass mode.Signed-off-by: Robin Gong
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I2C2 have to be disabled on hdcp board since those I2C2 bus pins
used for others, that said there is no all pmic regulators. In this
case, ldo-enable mode should be used and reg_arm/reg_soc/reg_pu should
be swithed to internal ldo instead. Otherwise, no reg_pu regulator
probed successfully by gpu driver, and cause gpu probe failed. Also,
cause cpufreq probe failed too.Signed-off-by: Robin Gong
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With current clock configuration we cannot derive bitclk for S20_3LE
format in SAI master mode. There was an attempt to fix this in commit
65e6b5f1b4a7 ("MLK-14536: ASoC: wm8960: Fix playback in CPU DAI master mode")
but this broke codec-master mode, thus the patch was partially reverted in
96f0d36e420 ("MLK-14798: arm: dts: imx6ul: Fix wm8960 codec master mode")So, remove S20_3LE support for SAI master mode. Clients using this
feature should use codec master mode, which is the default one in the
dts anyway.Signed-off-by: Daniel Baluta
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When 'CONFIG_MXC_PXP_CLIENT_DEVICE' disabled, the
'register_pxp_device' and 'unregister_pxp_device'
may cause multiple definitions compiling error.Signed-off-by: Fancy Fang
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For wm8962 we use imx-wm8962 machine driver which expects DAI CPU node
name to be "cpu-dai".Signed-off-by: Daniel Baluta
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The mem_base address is configured as the outbound
memory region twice when imx pcie ep/rc validation
is enabled.
Mask the one contained in desigware driver to fix
this issue.
Remove the usleep_range usage in designware driver,
since that function maybe used in imx noirq pm
calls.Signed-off-by: Richard Zhu
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pp->ops is not assigned properly, thus there
would be kernel panic when reboot ep board.
Initialized pp->ops in ep initializatione,
fix this issue.
don't call dw_pcie_wait_for_link because
the usleep is used in it.Signed-off-by: Richard Zhu
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There is error log "wm8962 3-001a: Unsupported BCLK ratio 6"
When the bitstream's format is S20_3LE.
The reason is that the pll output is samplerate*256, which
can't divide to clock samplerate*20*2. So in this patch change
the pll output to samplerate*384, and use the physical_width
for S20_3LE to calculate the bclk.Signed-off-by: Shengjiu Wang
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There is a bug in ssi sdma script cause dual fifo swap.Correct
it in sdma script.Signed-off-by: Robin Gong
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Commit 65e6b5f1b4a7 ("ASoC: wm8960: Fix playback in CPU DAI master
mode") broke wm8960 codec master mode by choosing "bad" SYSCLK values.This patch partially reverts commit mentioned above by restoring the
SYSCLK values. It turns out that using params_physical_width instead of
params_width in the previous patch it is enough to fix CPU DAI mode.Signed-off-by: Daniel Baluta
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This reverts commit c768ed336bba ("ASoC: fsl-sai: set xCR4/xCR5/xMR for
SAI master mode")This change was already introduced by commit 51659ca069ce ("ASoC: fsl-sai:
set xCR4/xCR5/xMR for SAI master mode") from upstream.Manually adjust the code to match the changes introduced by subsequent
commit b2936555bb38 ("MLK-13609: ASoC: fsl_sai: fix for synchronize mode")
by removing updates to FSL_SAI_TMR/FSL_SAI_RMR registers.Signed-off-by: Mihai Serban
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The latest pxp_dma.h file change PXP_PIX_FMT_RGB32 to PXP_PIX_FMT_XRGB32 format,
but the userspace still use PXP_PIX_FMT_RGB32, so add back it and keep the same
with PXP_PIX_FMT_XRGB32 format.Signed-off-by: Guoniu.Zhou
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Commit 556fa2d7d7e9 ("ENGR00318895-9: mtd: spi-nor: add more read
transfer flags for n25q256a") was incompletely cherry-picked, leaving
out the removal of the SECT_4K flag:"From the datasheet, the chip support the 64K sector erase operation.
So remove the SECT_4K for the chip which makes the flash_erase
faster."However, the above statement is not entirely correct. Using SECT_4K
can result in faster erase operations, if the block to erase is
smaller. The documentation in spi-nor.c also states:"All newly added entries should describe *hardware* and should use
SECT_4K (or SECT_4K_PMC) if hardware supports erasing 4 KiB
sectors. For usage scenarios excluding small sectors there is config
option that can be disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS. For
historical (and compatibility) reasons (before we got above config)
some old entries may be missing 4K flag."Unfortunately, using SECT_4K means that ubifs will fail, because it
needs a minimum LBE of 15K.Based on the above comments, it looks like the best way to handle the
ubifs issue is to disable CONFIG_MTD_SPI_NOR_USE_4K_SECTORS instead of
removing SECT_4K for the particular n25q256a chip. This approach also
has the advantage that will make ubifs work with any chip that has the
SECT_4K flag.Signed-off-by: Octavian Purdila
Reviewed-by: Han Xu -
Commit 665ced16cf044 ("MLK-10050 dma: imx-sdma: add support for sdma
memory copy") enforces maximum SDMA buffer descriptor length at 65532,
but doesn't update period_bytes_max or max_segment size in DMA drivers.Thus, resulting in the following bug:
$ arecord -Dhw:0,0 -r 192000 -f S20_3LE -c 1 -d 10 audio192k20b1c.wav
imx-sdma: SDMA channel 5: maximum period size exceeded: 65534 > 65532Signed-off-by: Daniel Baluta
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This is very similar to an older patch:
commit e1cbbcd1d1ac ("MLK-12161 tty: serial: imx: only enable RTSD
interrupt for hw flow control")The difference is that it adds the same check on the suspend path. This
fixes suspend not working on imx6sl-evk when uart wakeup is enabled.
What happens instead is that an interrupt is imediately received on the
suspend path.Signed-off-by: Leonard Crestez
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On this board RTS is not connected. Couldn't we ensure that no noise is
received using pinctrl settings?To: Fugang Duan
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Without this information probing of imx-rpmsg fails as it is not able
to setup the vring due to missing allocated physical memory.Signed-off-by: Octavian Purdila
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The V3 version PXP has added below new 2D features:
1. Input fetch/store blocks to accept different formats input/output.
2. Add Rotation1 block to do rotation before alpha blending.
3. Add Composite1 block to accept source from input fetch.
4. AS and PS have increased supported pixel formats.Signed-off-by: Fancy Fang
Signed-off-by: Guoniu.Zhou
(cherry picked from commit 4daef24b19890ca65135c48fc24018f64761444f) -
Based on the previously caculated adjacent list and mux
config info, the shortest path table can be derived by
distance calculation between two different 2D nodes.Signed-off-by: Fancy Fang
(cherry picked from commit c8adf0f7089d5c5e286d7ae74c138a84bed5e280) -
According to the PXP arch diagram, the V3 PXP can be
abstracted to a graph structure. There are totally
16 2D nodes in PXP and 16 2D related mux nodes:1. Using '16x16' adjacent array to record the 2D nodes
relationship and '16' size array to record the
input and output nodes for each muxe node.
2. Construct the adjacent list to store all the 2D
nodes and also config the mux info used by each
two nodes of one edge during pxp probing stage.Signed-off-by: Fancy Fang
(cherry picked from commit e8087406df2e04982fd90b4070ac68fafa4ad3d5) -
Extract the timer initialization from pxp_probe()
to a seperate function call to make probing process
more clear.Signed-off-by: Fancy Fang
(cherry picked from commit c8a127e506bca2e38fae02c03ceae4e6956d6ea3) -
Extract the attributes creation from the pxp_probe()
to a seperate function call to make the probing process
more clear.Signed-off-by: Fancy Fang
(cherry picked from commit 85ab5476bf59a407037b43419b920b681b58b52d) -
Extract the m4 related initialization code from
pxp_probe() to make the probing function more
clear.Signed-off-by: Fancy Fang
(cherry picked from commit f1bd8146332f880b75f08eab64505070069018fb) -
The PXP interrupt functions in V3 is relatively complex.
So do the interrupt initalization in a sperate function
to make the pxp_probe() more clear.Signed-off-by: Fancy Fang
(cherry picked from commit 2fa43d26f81cf0331820b41bc198adbb414c0c37) -
Remove some assignments which have no real effects for
V2 and V3 PXP drivers, since using devm_kzalloc() to
make the data to be zero.Signed-off-by: Fancy Fang
(cherry picked from commit a6d6e4d2b6b21427c529a33a7d47ddc918b19eb7) -
Add several new pixel formats definition which are supported
by PXP V3 ip.Signed-off-by: Fancy Fang
(cherry picked from commit 5195602ac0225902bd416647fb9cd0636fa11e89) -
Some RGB formats fourcc definition are not precise
according to its original meaning. So make some
changes for them.Signed-off-by: Fancy Fang
(cherry picked from commit b0b4ad680e267bdf542d2c9a3202c0192bde9cb0) -
According to the pxp high level architecture diagram,
it is better to divide the whole big pxp module into
four sub-modules:
1. 2D operation module(legacy pxp and input fetch & store).
2. Dithering module.
3. WFE_A module.
4. WFE_B module.
This division will simplify driver implementations and
management.Signed-off-by: Fancy Fang
(cherry picked from commit 5e57840b41adb195515bd652d9624feaadf3448e) -
Abstract PS and OUT formats parsing jobs to seperate
functions 'pxp_parse_ps_fmt()' and 'pxp_parse_out_fmt()'
to make the code clean and easier to maintain.Signed-off-by: Fancy Fang
(cherry picked from commit 3e2cd1880fdf219c77f119fa5c9fb33e50e8654c) -
Add 'need_yuv_swap' field to 'pxp_proc_data' structure to
record the yuv formats which needs byte swap.Signed-off-by: Fancy Fang
(cherry picked from commit 28ce43b27faad915e93f47b438d23f4ebfe020b5) -
Use 'switch' statement to replace 'if' statement to
make logic more clear and easier to maintain.Signed-off-by: Fancy Fang
(cherry picked from commit ca1b4393b86054a81bb40ad856af9c4f166841ea) -
The multiple overlay layers are not used on pxp v2 and
v3 module, so remove this.Signed-off-by: Fancy Fang
(cherry picked from commit c4fd8b36dbf9b53079d88d55ccfedde3a444ec29) -
Re-apply Dong Aisheng's patch for MLK-13190, as the issue
reappeared with bcmdhd update v1.141.100.6:BCMDHD_SDIO needs to be tristate for the correct dependency
of MMC core subsystem.
And the old driver buildin mode is static defined by DRIVER_TYPE.
Fix it to depend on CONFIG_BCMDHD_SDIO.Signed-off-by: Dong Aisheng
Signed-off-by: Tiberiu Breana -
which don't request the dma channel in the probe, but request
dma channel when needed. for the dma channel of cpu dai in BE
can be reused by the FE.Signed-off-by: Shengjiu Wang
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This reverts commit a87bb06a0bc7 that breaks busfreq test case.
Signed-off-by: Fugang Duan
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Set specific fmt for emulation build, for i2s xtor receiver is
in slave mode and i2s xtor transmitter is in master mode.Signed-off-by: Shengjiu Wang
Signed-off-by: Viorel Suman -
The SAI interface can be a clock supplier or consummer
as function of stream direction, ie when interacting
with I2S XTOR. Removed FSL_SAI_RFR define as it is now
referred as FSL_SAI_RFR0.Signed-off-by: Viorel Suman
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Many boards installed with i.MX chip only use two pins for mii bus
in two NET MAC system to save two pins. Then one MAC need to share
the mii bus with the other one. Since two net interface operation
are parallel and separate, we should keep the shared mii bus always
be active. So it should keep MAC clocks on.Signed-off-by: Fugang Duan
(cherry picked from commit: d0f18f7633ed)