10 Sep, 2020
1 commit
-
Add the ability to disable a link with a boolean parameter to the
link_enable function. This is necessary so that the master can disable
links that it isn't using; for example, links to slaves that fail
initialization.Signed-off-by: Eddie James
Signed-off-by: Joel Stanley
21 May, 2019
1 commit
-
Add SPDX license identifiers to all files which:
- Have no license information of any form
- Have MODULE_LICENCE("GPL*") inside which was used in the initial
scan/conversion to ignore the fileThese files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:GPL-2.0-only
Signed-off-by: Thomas Gleixner
Signed-off-by: Greg Kroah-Hartman
12 Jul, 2018
7 commits
-
This moves the definitions for various protocol details
(message & response codes, delays etc...) out of
fsi-master-gpio.c to fsi-master.h in order to share them
with other master implementations.Signed-off-by: Benjamin Herrenschmidt
Reviewed-by: Joel Stanley -
The embedded struct device needs a release function to be
able to successfully remove the driver.We remove the devm_gpiod_put() as they are unnecessary
(the resources will be released automatically) and because
fsi_master_unregister() will cause the master structure to
be freed.Signed-off-by: Benjamin Herrenschmidt
Reviewed-by: Joel Stanley -
Some definitions are generic to the FSI protocol or any
give master implementation. Rename them to remove the
"GPIO" prefix in preparation for moving them to a common
header.Signed-off-by: Benjamin Herrenschmidt
Reviewed-by: Joel Stanley# Conflicts:
# drivers/fsi/fsi-master-gpio.c -
Signed-off-by: Benjamin Herrenschmidt
Reviewed-by: Joel Stanley -
This adds a few more tracepoints that have proven useful when
debugging issues with the FSI bus.This also makes echo_delay() use clock_zeros() instead of
open-code it in order to share the tracepoint.Signed-off-by: Benjamin Herrenschmidt
Reviewed-by: Joel Stanley -
To configure the send and echo delays
Signed-off-by: Benjamin Herrenschmidt
Reviewed-by: Joel Stanley -
What the driver called "FSI_GPIO_PRIME_SLAVE_CLOCKS" is what
the FSI spec calls tSendDelay and should be 16 clocks by
default.Signed-off-by: Benjamin Herrenschmidt
Reviewed-by: Joel Stanley
12 Jun, 2018
13 commits
-
We currently use a spinlock (bit_lock) around operations that clock bits
out of the FSI bus, and a mutex to protect against simultaneous access
to the master.This means that bit_lock isn't needed for mutual exlusion, only to
prevent timing issues when clocking bits out.To reflect this, this change converts bit_lock to just the
local_irq_save/restore operation.Signed-off-by: Jeremy Kerr
Signed-off-by: Benjamin Herrenschmidt
Tested-by: Joel Stanley -
Remove calls to the empty and useless fsi_master_gpio_error()
function, and report CRC errors as "FSI_ERR_NO_SLAVE" when
reading an all 1's response.Signed-off-by: Benjamin Herrenschmidt
Tested-by: Joel Stanley -
The FSI protocol defines two modes of recovery from CRC errors,
this implements both:- If the device returns an ECRC (it detected a CRC error in the
command), then we simply issue the command again.- If the master detects a CRC error in the response, we send
an E_POLL command which requests a resend of the response
without actually re-executing the command (which could otherwise
have unwanted side effects such as dequeuing a FIFO twice).Signed-off-by: Benjamin Herrenschmidt
Reviewed-by: Christopher Bostic
Tested-by: Joel Stanley
---Note: This was actually tested by removing some of my fixes, thus
causing us to hit occasional CRC errors during high LPC activity. -
FSI CFAMs support shorter commands that use a relative (or same) address
as the last. This change introduces a last_addr to the master state, and
uses it for subsequent reads/writes, and performs relative addressing
when a subsequent read/write is in range.Signed-off-by: Jeremy Kerr
Signed-off-by: Benjamin Herrenschmidt
Reviewed-by: Christopher Bostic
Tested-by: Joel Stanley -
For implementing relative addressing mode, we'll need to build a command
that is coherent with CFAM state. To do that, include the
build_command_* functions in the locked section of read/write/term.Signed-off-by: Jeremy Kerr
Signed-off-by: Benjamin Herrenschmidt
Tested-by: Joel Stanley -
Most SoC GPIO implementations, including the Aspeed one, have
synchronizers on the GPIO inputs. This means that the value
read from a GPIO is a couple of clocks old, from whatever clock
source feeds those synchronizers.In practice, this means that in no-delay mode, we are using a
value that can potentially be a bit too old and too close to
the clock edge establishing the data on the other side of the link.The voltage converters we use on some systems make this worse
and sensitive to things like voltage fluctuations etc... This is,
we believe, the cause of occasional CRC errors encountered during
heavy activity on the LPC bus.This is fixed by introducing a dummy GPIO read before the actual
data read. It slows down SBEFIFO by about 15% (less than any delay
primitive) and the end result is so far solid.Signed-off-by: Benjamin Herrenschmidt
Reviewed-by: Christopher Bostic
Tested-by: Joel Stanley -
FSI_GPIO_DPOLL_CLOCKS is the number of clocks before sending
a DPOLL command after receiving a BUSY status. It should be
at least tSendDelay (16 clocks).According to comments in the code, it needs to also be at least
21 clocks due to HW issues.It's currently 100 clocks which impacts performances negatively
in some cases. Reduces it in half to 50 clocks which seems to
still be solid.Signed-off-by: Benjamin Herrenschmidt
Reviewed-by: Christopher Bostic
Tested-by: Joel Stanley -
FSI_GPIO_PRIME_SLAVE_CLOCKS is the number of clocks if the
"idle" phase between the end of a response and the beginning
of the next one. It corresponds to tSendDelay in the FSI
specification.The default value in the slave is 16 clocks. 100 is way overkill
and significantly reduces the driver performance.This changes it to 20 (which gives the HW a bit of margin still
just in case).Signed-off-by: Benjamin Herrenschmidt
Reviewed-by: Christopher Bostic
Tested-by: Joel Stanley -
This adds support for an optional device-tree property that
makes the driver skip all the delays around clocking the
GPIOs and set it in the device-tree of common POWER9 based
OpenPower platforms.This useful on chips like the AST2500 where the GPIO block is
running at a fairly low clock frequency (25Mhz typically). In
this case, the delays are unnecessary and due to the low
precision of the timers, actually quite harmful in terms of
performance.Signed-off-by: Benjamin Herrenschmidt
Reviewed-by: Christopher Bostic
Tested-by: Joel Stanley -
We currently sample the input data right after we toggle the
clock low, then high. The slave establishes the data on the
rising edge, so this is not ideal. We should sample it on
the low phase instead.This currently works because we have an extra delay, but subsequent
patches will remove it.Signed-off-by: Benjamin Herrenschmidt
Reviewed-by: Christopher Bostic
Tested-by: Joel Stanley -
Reduce time spent with interrupts disabled by limiting the critical
sections to bitbanging FSI symbols. We only need to ensure exclusive use
of the bus for an entire transfer, not that the transfer be performed in
atomic context.Signed-off-by: Jeremy Kerr
Signed-off-by: Benjamin Herrenschmidt
Tested-by: Joel Stanley -
Signed-off-by: Andrew Jeffery
Signed-off-by: Benjamin Herrenschmidt
Tested-by: Joel Stanley -
An observation from trace output of the existing FSI tracepoints was
that the remote device was sometimes reporting as busy. Add a new
tracepoint reporting the busy count in order to get a better grip on how
often this is the case.Signed-off-by: Andrew Jeffery
Acked-by: Eddie James
Signed-off-by: Benjamin Herrenschmidt
Tested-by: Joel Stanley
15 Mar, 2018
3 commits
-
This change populates device tree nodes for scanned FSI slaves and
engines. If the master populates ->of_node of the FSI master device,
we'll look for matching slaves, and under those slaves we'll look for
matching engines.This means that FSI drivers will have their ->of_node pointer populated
if there's a corresponding DT node, which they can use for further
device discover.Presence of device tree nodes is optional, and only required for
fsi device drivers that need extra properties, or subordinate devices,
to be enumerated.Signed-off-by: Jeremy Kerr
Signed-off-by: Joel Stanley
Signed-off-by: Greg Kroah-Hartman -
This change introduces an 'external mode' for GPIO-based FSI masters,
allowing the clock and data lines to be driven by an external source.
For example, external mode is selected by a user when an external debug
device is attached to the FSI pins.To do this, we need to set specific states for the trans, mux and enable
GPIOs, and prevent access to clk & data from the FSI core code (by
returning EBUSY).External mode is controlled by a sysfs attribute, so add the relevant
information to Documentation/ABI/Signed-off-by: Jeremy Kerr
Reviewed-by: Joel Stanley
Signed-off-by: Joel Stanley
Signed-off-by: Greg Kroah-Hartman -
Currently, we perform GPIO accesses in fsi_master_gpio_break and
fsi_master_link_enable, without holding cmd_lock. This change adds the
appropriate locking.Signed-off-by: Jeremy Kerr
Reviewed-by: Joel Stanley
Reviewed-by: Christopher Bostic
Signed-off-by: Joel Stanley
Signed-off-by: Greg Kroah-Hartman
09 Jun, 2017
3 commits
-
For slaves that are behind a software-clocked master, we want FSI CFAMs
to run asynchronously to the FSI clock, so set up our slaves to be in
async mode.Signed-off-by: Jeremy Kerr
Signed-off-by: Christopher Bostic
Signed-off-by: Greg Kroah-Hartman -
Trace low level input/output GPIO operations.
Signed-off-by: Jeremy Kerr
Signed-off-by: Christopher Bostic
Signed-off-by: Greg Kroah-Hartman -
Implement a FSI master using GPIO. Will generate FSI protocol for
read and write commands to particular addresses. Sends master command
and waits for and decodes a slave response.Includes changes from Edward A. James and Jeremy
Kerr .Signed-off-by: Edward A. James
Signed-off-by: Jeremy Kerr
Signed-off-by: Christopher Bostic
Signed-off-by: Joel Stanley
Signed-off-by: Greg Kroah-Hartman
