30 Dec, 2020

1 commit

  • [ Upstream commit 03fc41afaa6549baa2dab7a84e1afaf5cadb5b18 ]

    pm_runtime_get_sync will increment pm usage counter even it
    failed. Forgetting to pm_runtime_put_noidle will result in
    reference leak in mxs_spi_probe, so we should fix it.

    Fixes: b7969caf41a1d ("spi: mxs: implement runtime pm")
    Signed-off-by: Zhang Qilong
    Link: https://lore.kernel.org/r/20201106012421.95420-1-zhangqilong3@huawei.com
    Signed-off-by: Mark Brown
    Signed-off-by: Sasha Levin

    Zhang Qilong
     

17 Mar, 2020

1 commit

  • This driver is not using any symbols from the GPIO .h files
    so drop them.

    It was however implicitly using
    so include that instead.

    Cc: Fabio Estevam
    Signed-off-by: Linus Walleij
    Link: https://lore.kernel.org/r/20200317092457.264055-1-linus.walleij@linaro.org
    Signed-off-by: Mark Brown

    Linus Walleij
     

16 Dec, 2019

1 commit


05 Sep, 2019

1 commit


29 Jan, 2019

1 commit


03 May, 2018

1 commit


28 Sep, 2017

1 commit

  • This is a straight forward addition of runtime and system sleep pm operations
    that handle clk and pinctrl (for runtime pm) and spi_master_{suspend,resume}
    (for system sleep).

    Signed-off-by: Uwe Kleine-König
    Signed-off-by: Mark Brown

    Uwe Kleine-König
     

06 Feb, 2015

1 commit


15 Dec, 2014

1 commit

  • Pull driver core update from Greg KH:
    "Here's the set of driver core patches for 3.19-rc1.

    They are dominated by the removal of the .owner field in platform
    drivers. They touch a lot of files, but they are "simple" changes,
    just removing a line in a structure.

    Other than that, a few minor driver core and debugfs changes. There
    are some ath9k patches coming in through this tree that have been
    acked by the wireless maintainers as they relied on the debugfs
    changes.

    Everything has been in linux-next for a while"

    * tag 'driver-core-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (324 commits)
    Revert "ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries"
    fs: debugfs: add forward declaration for struct device type
    firmware class: Deletion of an unnecessary check before the function call "vunmap"
    firmware loader: fix hung task warning dump
    devcoredump: provide a one-way disable function
    device: Add dev__once variants
    ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries
    ath: use seq_file api for ath9k debugfs files
    debugfs: add helper function to create device related seq_file
    drivers/base: cacheinfo: remove noisy error boot message
    Revert "core: platform: add warning if driver has no owner"
    drivers: base: support cpu cache information interface to userspace via sysfs
    drivers: base: add cpu_device_create to support per-cpu devices
    topology: replace custom attribute macros with standard DEVICE_ATTR*
    cpumask: factor out show_cpumap into separate helper function
    driver core: Fix unbalanced device reference in drivers_probe
    driver core: fix race with userland in device_add()
    sysfs/kernfs: make read requests on pre-alloc files use the buffer.
    sysfs/kernfs: allow attributes to request write buffer be pre-allocated.
    fs: sysfs: return EGBIG on write if offset is larger than file size
    ...

    Linus Torvalds
     

25 Nov, 2014

1 commit

  • We can only use page_address on memory that has been mapped using kmap,
    when the buffer passed to the SPI has been allocated by vmalloc the page
    has not necessarily been mapped through kmap. This means sometimes
    page_address will return NULL causing the pointer we pass to sg_init_one
    to be invalid. Currently, this issue doesn't show up on the MXS
    architecture as the defconfig defines CONFIG_HIGHMEM=n which means all
    pages are mapped. For the sake of robustness though it is best to
    correct the issue.

    As we only call page_address so that we can pass a virtual address to
    sg_init_one which will eventually call virt_to_page on it, fix this
    by calling sg_set_page directly rather then relying on the sg_init_one
    helper.

    Note this patch is only build tested as I don't have an MXS system to
    test on.

    Signed-off-by: Charles Keepax
    Signed-off-by: Mark Brown

    Charles Keepax
     

11 Nov, 2014

1 commit

  • Instead of registering the irq name with the driver name, it's better to pass
    the device name so that we have a more explicit indication as to what spi
    instance the irq is related:

    $ cat /proc/interrupts
    CPU0
    ...
    27: 0 - 98 80014000.ssp

    Signed-off-by: Fabio Estevam
    Signed-off-by: Mark Brown

    Fabio Estevam
     

20 Oct, 2014

1 commit


03 Oct, 2014

2 commits


03 Sep, 2014

1 commit

  • Fix the following checkpatch warnings.

    WARNING: Missing a blank line after declarations
    WARNING: Prefer kcalloc over kzalloc with multiply

    Signed-off-by: Jingoo Han
    Acked-by: Marek Vasut
    Signed-off-by: Mark Brown

    Jingoo Han
     

30 Mar, 2014

1 commit


15 Feb, 2014

1 commit


07 Feb, 2014

1 commit


03 Feb, 2014

1 commit


17 Jan, 2014

1 commit


28 Nov, 2013

1 commit


18 Nov, 2013

1 commit


15 Nov, 2013

1 commit


25 Oct, 2013

1 commit


18 Oct, 2013

13 commits

  • It's consistent with all the other spi drivers that way.

    Signed-off-by: Trent Piepho
    Cc: Marek Vasut
    Cc: Fabio Estevam
    Cc: Shawn Guo
    Signed-off-by: Mark Brown

    Trent Piepho
     
  • mxs_spi_setup_transfer() would set the SSP SCK rate every time it was
    called, which is before every transfer. It is uncommon for the SCK rate to
    change between transfers (or at all of that matter) and this causes many
    unnecessary reprogrammings of the clock registers.

    Code changed to only set the rate when it changes. This significantly
    speeds up short SPI messages, especially messages made up of many transfers,
    as the calculation of the clock divisors is rather costly. On an iMX287,
    using spidev with messages that consist of 511 transfers of 4 bytes each at
    an SCK of 48 MHz, the effective transfer rate more than doubles from about
    290 KB/sec to 600 KB/sec!

    Signed-off-by: Trent Piepho
    Cc: Marek Vasut
    Cc: Fabio Estevam
    Cc: Shawn Guo
    Signed-off-by: Mark Brown

    Trent Piepho
     
  • It can't be called with a NULL transfer anymore so it can be simplified
    to not check for that.

    Fix indention of line-wrapped code to Linux standard.

    The transfer pointer can be const.

    It's not necessary to check if the spi_transfer's speed_hz is zero, as
    the spi core also fills it in from the spi_device. However, the spi
    core does not check if spi_device's speed is zero so we have to do
    that still.

    Signed-off-by: Trent Piepho
    Cc: Marek Vasut
    Cc: Fabio Estevam
    Cc: Shawn Guo
    Signed-off-by: Mark Brown

    Trent Piepho
     
  • The spi core already checks for a slave setting mode bits that we
    didn't list as supported when the master was registered. There is no
    need to do it again in the master driver.

    Signed-off-by: Trent Piepho
    Cc: Marek Vasut
    Cc: Fabio Estevam
    Cc: Shawn Guo
    Signed-off-by: Mark Brown

    Trent Piepho
     
  • Despite many warnings in the SPI documentation and code, the spi-mxs
    driver sets shared chip registers in the ->setup method. This method can
    be called when transfers are in progress on other slaves controlled by the
    master. Setting registers or any other shared state will corrupt those
    transfers.

    So fix mxs_spi_setup() to not call mxs_spi_setup_transfer().
    mxs_spi_setup_transfer() is already called for each transfer when they
    are actually performed in mxs_spi_transfer_one(), so the call in
    mxs_spi_setup() isn't necessary to setup anything.

    Signed-off-by: Trent Piepho
    Cc: Marek Vasut
    Cc: Fabio Estevam
    Cc: Shawn Guo
    Signed-off-by: Mark Brown

    Trent Piepho
     
  • The ssp struct has a clock rate field, to provide the actual value, in Hz,
    of the SSP output clock (the rate of SSP_SCK) after mxs_ssp_set_clk_rate()
    is called. It is set by mxs_ssp_set_clk_rate(), for SSP using drivers (like
    SPI and MMC) to *read* if they want to know the actual clock rate. The SPI
    driver isn't supposed to *write* to it.

    For some reason the spi-mxs driver decides to write to this field on init,
    and sets it to the value of the SSP input clock (clk_sspN, from the MXS
    clocking block) in kHz. It shouldn't be setting the value, and certainly
    shouldn't be setting it with the wrong clock in the wrong units.

    Signed-off-by: Trent Piepho
    Cc: Marek Vasut
    Cc: Fabio Estevam
    Cc: Shawn Guo
    Signed-off-by: Mark Brown

    Trent Piepho
     
  • Because the driver sets the SPI_MASTER_HALF_DUPLEX flag, the spi core
    will check transfers to insure they are not full duplex. It's not
    necessary to check that in the spi-mxs driver as well.

    Signed-off-by: Trent Piepho
    Cc: Marek Vasut
    Cc: Fabio Estevam
    Cc: Shawn Guo
    Signed-off-by: Mark Brown

    Trent Piepho
     
  • In DMA mode the chip select control bits would be ORed into the CTRL0
    register without first clearing the bits. This means that after
    addressing slave 1, the CTRL0 bit to address slave 1 would be still be
    set when addressing slave 0, resulting in slave 1 continuing to be
    addressed.

    The message handling function would pass the CS value to the txrx
    function, which would re-program the bits on each transfer in the
    message. The selected CS does not change during a message so this is
    inefficient. It also means there are two different sets of code for
    selecting the CS, one for PIO that worked and one for DMA that didn't.

    Change the code to set the CS bits in the message handling function
    once. Now the DMA and PIO txrx functions don't need to care about CS
    at all.

    Signed-off-by: Trent Piepho
    Cc: Marek Vasut
    Cc: Fabio Estevam
    Cc: Shawn Guo
    Signed-off-by: Mark Brown

    Trent Piepho
     
  • There are two bits which control the CS line in the CTRL0 register:
    LOCK_CS and IGNORE_CRC. The latter would be better named DEASSERT_CS
    in SPI mode.

    Setting DEASSERT_CS causes CS to be de-asserted at the end of the transfer.
    It should normally be set only for the final segment of the final transfer.
    The DMA code explicitly sets it in this case, but because it never clears
    the bit from the ctrl0 register, it will remain set for all transfers in
    subsequent messages. This results in a CS pulse between transfers.

    There is a similar problem with the read mode bit never being cleared
    in DMA mode.

    This patch fixes DEASSERT_CS and READ being left on in DMA mode.

    Signed-off-by: Trent Piepho
    Cc: Marek Vasut
    Cc: Fabio Estevam
    Cc: Shawn Guo
    Signed-off-by: Mark Brown

    Trent Piepho
     
  • There are three flag arguments to the PIO and DMA txrx functions. Two
    are passed as pointers to integers, even though they are input only
    and not modified, which makes no sense to do. The third is passed as
    an integer.

    The compiler must use an argument register or stack variable for each
    flag this way. Using bitflags in a single flag argument is more
    efficient and produces smaller code, since all the flags can fit in a
    single register. And all the flag arguments get cumbersome,
    especially when more are added for things like GPIO chipselects.

    The "first" flag is never used, so can just be deleted.

    The "last" flag is renamed to DEASSERT_CS, since that's really what it
    does. The spi_transfer cs_change flag means that CS might be
    de-asserted on a transfer which is not last and not de-assert on the
    last transfer, so it is not which transfer is the last we need to know
    but rather the transfers after which CS should be de-asserted.

    This also extends the driver to not ignore cs_change when setting the
    DEASSERT_CS nee "last" flag.

    Signed-off-by: Trent Piepho
    Cc: Marek Vasut
    Cc: Fabio Estevam
    Cc: Shawn Guo
    Signed-off-by: Mark Brown

    Trent Piepho
     
  • INGORE_CRC, better named DEASSERT_CS, should be cleared on all tranfers
    except the last. So instead of only clearing it on the first transfer, we
    can just always clear it. It will set on the last transfer.

    This removes the only use of the "first" flag in the transfer functions, so
    that flag can be then be removed.

    Signed-off-by: Trent Piepho
    Cc: Marek Vasut
    Cc: Fabio Estevam
    Cc: Shawn Guo
    Signed-off-by: Mark Brown

    Trent Piepho
     
  • These functions consist of nothing but one single writel call and are
    only called once. And the names really aren't accurate or clear,
    since they don't enable or disble SPI. Rather they set the bit that
    controls the state of CS at the end of transfer. It easier to follow
    the code to just set this bit with a writel() along with all the other
    bits being set in the same function.

    Signed-off-by: Trent Piepho
    Cc: Marek Vasut
    Cc: Fabio Estevam
    Cc: Shawn Guo
    Signed-off-by: Mark Brown

    Trent Piepho
     
  • There are two bits which control the CS line in the CTRL0 register:
    LOCK_CS and IGNORE_CRC. The latter would be better named DEASSERT_CS
    in SPI mode.

    LOCK_CS keeps CS asserted though the entire transfer. This should
    always be set. The DMA code will always set it, explicitly on the
    first segment of the first transfer, and then implicitly on all the
    rest by never clearing the bit from the value read from the ctrl0
    register.

    The PIO code will explicitly set it for the first transfer, leave it
    set for intermediate transfers, and then clear it for the final
    transfer. It should not clear it.

    The only reason to not set LOCK_CS would be to attempt an altered
    protocol where CS pulses between each word. Though don't get your
    hopes up if you want to do this, as the hardware doesn't appear to do
    this in any sane manner. It appears to be related to the hardware
    FIFO fill level.

    The code can be simplified by just setting LOCK_CS once and then not
    needing to deal with it at all in the PIO and DMA transfer functions.

    Signed-off-by: Trent Piepho
    Cc: Marek Vasut
    Cc: Fabio Estevam
    Cc: Shawn Guo
    Signed-off-by: Mark Brown

    Trent Piepho
     

26 Sep, 2013

1 commit


07 Aug, 2013

1 commit


22 Jul, 2013

1 commit