27 Oct, 2015
2 commits
-
The complexity of the boot sequence of UniPhier SoC family is
a PITA due to the following hardware limitations:[1] No dedicated on-chip SRAM
SoCs in general have small SRAM, on which a tiny firmware or a boot
loader can run before SDRAM is initialized. As UniPhier SoCs do not
have any dedicated SRAM accessible from CPUs, the locked outer cache
is used instead. Due to the ARM specification, to have access to
the outer cache, the MMU must be enabled. This is done for all CPU
cores by the program hard-wired in the boot ROM. The boot ROM code
loads a small amount of program (this is usually SPL of U-Boot) from
a non-volatile device onto the locked outer cache, and the primary
CPU jumps to it. The secondary CPUs stay in the boot ROM until they
are kicked by the primary CPU.[2] CPUs can not directly jump to SDRAM address space
As mentioned above, the MMU is enable for all the CPUs with the page
table hard-wired in the boot ROM. Unfortunately, the page table only
has minimal sets of valid sections; all the sections of SDRAM address
space are zero-filled. That means all the CPUs, including secondary
ones, can not jump directly to SDRAM address space. So, the primary
CPU must bring up secondary CPUs to accessible address mapped onto
the outer cache, then again kick them to SDRAM address space.Before this commit, this complex task was done with help of a boot
loader (U-Boot); U-Boot SPL brings up the secondary CPUs to the entry
of U-Boot SPL and they stay there until they are kicked by Linux.
This is not nice because a boot loader must put the secondary CPUs
into a certain state expected by the kernel. It makes difficult to
port another boot loader because the boot loader and the kernel must
work in sync to wake up the secondary CPUs.This commit reworks the SMP operations so that they do not rely on
particular boot loader implementation; the SMP operations (platsmp.c)
put trampoline code (headsmp.S) on a locked way of the outer cache.
The secondary CPUs jump from the boot ROM to secondary_entry via the
trampoline code. The boot loader no longer needs to take care of SMP.Signed-off-by: Masahiro Yamada
Signed-off-by: Olof Johansson -
This commit adds support for UniPhier outer cache controller.
All the UniPhier SoCs are equipped with the L2 cache, while the L3
cache is currently only integrated on PH1-Pro5 SoC.Signed-off-by: Masahiro Yamada
Acked-by: Rob Herring
Signed-off-by: Olof Johansson
26 Oct, 2015
4 commits
-
…inux-samsung into next/soc
Samsung SoC updates for v4.4
- use PWM lookup table with pwm_add_table() for the following boards
: s3c24xx h1940 and rx1950
: s3c64xx smdk6410, crag6410, hmt and smartq
- document: update bootloader interface on exynos542x* tag 'samsung-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
Documentation: EXYNOS: Update bootloader interface on exynos542x
ARM: S3C64XX: Use PWM lookup table for mach-smartq
ARM: S3C64XX: Use PWM lookup table for mach-hmt
ARM: S3C64XX: Use PWM lookup table for mach-crag6410
ARM: S3C64XX: Use PWM lookup table for smdk6410
ARM: S3C24XX: Use PWM lookup table for mach-rx1950
ARM: S3C24XX: Use PWM lookup table for mach-h1940Signed-off-by: Olof Johansson <olof@lixom.net>
-
mvebu soc for 4.4 (part 2)
- Use mac_pton() helper in the oropn5x board instead of duplicating it
- Add the broken-idle option allowing to boot boards with a mistake in
the hardware design* tag 'mvebu-soc-4.4-2' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: add broken-idle option
ARM: orion5x: use mac_pton() helperSigned-off-by: Olof Johansson
-
…egra/linux into next/soc
ARM: tegra: Core SoC changes for v4.4-rc1
A single patch to restore rfkill support on AC100.
* tag 'tegra-for-4.4-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: paz00: use con_id's to refer GPIO's in gpiod_lookup tableSigned-off-by: Olof Johansson <olof@lixom.net>
-
…ni/linux into next/soc
More SoC changes for 4.4:
- a great fix for PM/suspend/resume* tag 'at91-ab-soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux:
ARM: at91: pm: at91_pm_suspend_in_sram() must be 8-byte alignedSigned-off-by: Olof Johansson <olof@lixom.net>
24 Oct, 2015
3 commits
-
…o/linux into next/soc
The i.MX SoC updates for 4.4:
- Enable suspend and cpufreq support for i.MX6UL
- Add platform level ENET initialization support for i.MX7D* tag 'imx-soc-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: imx: add cpufreq device for imx6ul
ARM: imx: add enet init for i.MX7D platform
ARM: imx7d: add imx7d iomux-gpr field define
ARM: imx: add suspend/resume support for i.mx6ulSigned-off-by: Olof Johansson <olof@lixom.net>
-
Do the initial setting of the pmic wrap interrupt before requesting the interrupt.
This fixes the corner-case where the pmic is initialized by the bootloader, but
not the pmic watchdog.Add support for active wakeup to the scpsys. This allows to keep the power of
a scpsys domain during suspend state.With version v4.3 new subsystem clocks are added to the clock dirver. In late
init the kernel turns off all unused clocks. This can provoke a hang if
the kernel tries to access the venc and venc_lt power domain registers.
Add the necessary parent clocks for this power domains to
the scpsys so that no random hang happens.The bootloader of mt6589, mt8135 and mt1827 does not turn on the arm-arch-timer.
As there is no opensource bootloader in the near future for this architectures
we enable the arch timer at kernel boot. We need the arch timer for SMP boot.Add support for SMP on mt6589, mt8127 and mt8135.
* tag 'v4.3-next-soc' of https://github.com/mbgg/linux-mediatek:
ARM: mediatek: add smp bringup code
ARM: mediatek: enable gpt6 on boot up to make arch timer working
soc: mediatek: Fix random hang up issue while kernel init
soc: mediatek: add scpsys support active_wakeup
soc: mediatek: Move the initial setting of pmic wrap interrupt before requesting irq.Signed-off-by: Olof Johansson
-
…t/mripard/linux into next/soc
Allwinner core changes for 4.4
Add support for the Allwinner R8 SoC used in the CHIP.
* tag 'sunxi-core-for-4.4' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
ARM: sunxi: Add R8 supportSigned-off-by: Olof Johansson <olof@lixom.net>
23 Oct, 2015
2 commits
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The broken-idle option can be activated from the coherency-fabric DT
node. This property allows to disable the idle capability, when the
hardware doesn't support it, like the Seagate Personal Cloud boards.Signed-off-by: Vincent Donnefort
Signed-off-by: Gregory CLEMENT -
Instead of custom approach let's use generic helper function.
Signed-off-by: Andy Shevchenko
Cc: Detlef Vollmann
Cc: Gregory CLEMENT
Tested-by: Tested-by: Detlef Vollmann #on DNS-323
Signed-off-by: Gregory CLEMENT
20 Oct, 2015
1 commit
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fncpy() requires that the source and the destination are both 8-byte
aligned.Signed-off-by: Patrick Doyle
Signed-off-by: Alexandre Belloni
Acked-by: Nicolas Ferre
Fixes: d94e688cae56 ("ARM: at91/pm: move the copying the sram function to the sram initialization phase")
Cc: # 4.1+
18 Oct, 2015
1 commit
-
The R8 is a new Allwinner SoC based on the A13. While both are very
similar, there's still a few differences. Introduce a new compatible to
deal with them.In order to have a consistent naming, instead of mentioning the Allwinner
A series as the machine name, switch to sun4i/sun5i like what is done for
the other families.Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
Reviewed-by: Chen-Yu Tsai
Acked-by: Stephen Boyd
16 Oct, 2015
8 commits
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…-berlin into next/soc
Merge "Marvell Berlin SoC for 4.4 take 2" from Sebastian Hesselbarth:
- use the non-self-clearing reset register
- add cpu hotplug support* tag 'berlin-soc-for-4.4-2' of git://git.infradead.org/users/hesselba/linux-berlin:
arm: berlin: add CPU hotplug support
arm: berlin: use non-self-cleared reset register to reset cpu -
Signed-off-by: Baruch Siach
Signed-off-by: Arnd Bergmann -
Merge "Broadcom soc changes for v4.4 (try 2)" from Florian Fainelli:
This pull request contains the following Broadcom SoC platform and driver changes:
- Brian Norris create a drivers/soc/brcmstb/ stub as a place holder for SoC-specific
code which is coming next- Florian Fainelli adds support for configuring the BCM7xxx SoCs Bus Interface Unit
with their specific write-pairing setting, which must be saved and restored during
system-wide suspend/resume, and consequently updates the brcmstb machine code to
initialize the BIU- Jon Mason adds support for the Northstar Plus SoCs by introducing a custom machine
descriptor matching their compatible string and setting up the PL310 L2 cache and
enabling the relevant ARM errata for their Cortex-A9* tag 'arm-soc/for-4.4/soc' of http://github.com/Broadcom/stblinux:
ARM: brcmstb: Setup BIU control registers during boot
soc: brcmstb: Add Bus Interface Unit control setup
soc: add stubs for brcmstb SoC's
ARM: NSP: Add basic support for Broadcom Northstar Plus SoC -
…-berlin into next/soc
Merge "Marvell SoC for 4.4 take 1" from Sebastian Hesselbarth:
- register cpufreq-dt device* tag 'berlin-soc-for-4.4-1' of git://git.infradead.org/users/hesselba/linux-berlin:
ARM: berlin: register cpufreq-dt -
…ux-berlin into next/soc
Merge "Marvell Berlin ARM64 SoC for 4.4 take 1" from Sebastian Hesselbarth:
- enable ARCH_REQUIRE_GPIOLIB for DW GPIO driver* tag 'berlin64-soc-for-4.4-1' of git://git.infradead.org/users/hesselba/linux-berlin:
arm64: berlin: enable ARCH_REQUIRE_GPIOLIB -
Merge "mvebu soc for 4.4 (part 1)" from Gregory CLEMENT:
L2 caches optimization for Armada XP
* tag 'mvebu-soc-4.4-1' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: add support to clear shared L2 bit on Armada XP -
Add cpu hotplug support for berlin SoCs such as BG2 and BG2Q. These SoC
don't support power off cpu independently, but we also want cpu hotplug
support in these SoCs. We achieve this goal by putting the dying CPU in
WFI state after the coherency is disabled, then asserting the dying CPU
reset bit to put the CPU in reset state.Signed-off-by: Jisheng Zhang
Signed-off-by: Sebastian Hesselbarth -
In Berlin SoCs, there are two kinds of cpu reset control registers: the
first one's corresponding bits will be self-cleared after some cycles,
while the second one's bits won't. Previously the first kind of reset
control register is used, this patch uses the second kind one to prepare
for the next hotplug commit.Signed-off-by: Jisheng Zhang
Signed-off-by: Sebastian Hesselbarth
14 Oct, 2015
2 commits
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Add support for booting secondary CPUs on mt6589, mt8127
and mt8135.Signed-off-by: Yingjoe Chen
Signed-off-by: Matthias Brugger -
We enable GTP6 which ungates the arch timer clock.
In the future this should be done in the bootloader.Signed-off-by: Matthias Brugger
Signed-off-by: Yingjoe Chen
13 Oct, 2015
6 commits
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Use a PWM lookup table to provide the PWM to the pwm-backlight device.
The driver has a legacy code path that is required only because boards
still use the legacy method of requesting PWMs by global ID. Replacing
these usages allows that legacy fallback to be removed.Signed-off-by: Thierry Reding
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Kukjin Kim -
Use a PWM lookup table to provide the PWM to the pwm-backlight device.
The driver has a legacy code path that is required only because boards
still use the legacy method of requesting PWMs by global ID. Replacing
these usages allows that legacy fallback to be removed.Signed-off-by: Thierry Reding
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Kukjin Kim -
Use a PWM lookup table to provide the PWM to the pwm-backlight device.
The driver has a legacy code path that is required only because boards
still use the legacy method of requesting PWMs by global ID. Replacing
these usages allows that legacy fallback to be removed.Signed-off-by: Thierry Reding
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Kukjin Kim -
Use a PWM lookup table to provide the PWM to the pwm-backlight device.
The driver has a legacy code path that is required only because boards
still use the legacy method of requesting PWMs by global ID. Replacing
these usages allows that legacy fallback to be removed.Signed-off-by: Thierry Reding
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Kukjin Kim -
Use a PWM lookup table to provide the PWM to the pwm-backlight device.
The driver has a legacy code path that is required only because boards
still use the legacy method of requesting PWMs by global ID. Replacing
these usages allows that legacy fallback to be removed.Signed-off-by: Thierry Reding
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Kukjin Kim -
Use a PWM lookup table to provide the PWM to the pwm-backlight device.
The driver has a legacy code path that is required only because boards
still use the legacy method of requesting PWMs by global ID. Replacing
these usages allows that legacy fallback to be removed.Signed-off-by: Thierry Reding
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Kukjin Kim
12 Oct, 2015
1 commit
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Add cpufreq device for i.MX6UL. Using the common
cpufreq of i.MX6 SOC.Signed-off-by: Bai Ping
Signed-off-by: Shawn Guo
10 Oct, 2015
1 commit
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Call brcmstb_biuctrl_init() in brcmstb's init_irq machine descriptor
callback since we need to setup the Bus Interface Unit before SMP in
particular, but we also need to be able to remap registers.Acked-by: Gregory Fong
Signed-off-by: Florian Fainelli
08 Oct, 2015
1 commit
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Signed-off-by: Carlo Caione
Signed-off-by: Arnd Bergmann
06 Oct, 2015
2 commits
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…ux-at91 into next/soc
Merge "First little batch of SoC changes for 4.4" from Nicolas Ferre:
- a MAINTAINER addition to cover SAMA5 SoCs
- removal of one unneeded header file
- for low-level serial output, use the DEBUG_UART_PHYS* tag 'at91-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91:
ARM: at91: debug: use DEBUG_UART_PHYS
ARM: at91: remove useless includes in platform_data/atmel.h
MAINTAINERS: explicitly add Atmel SAMA5 -
…t/horms/renesas into next/soc
Merge "Renesas ARM Based SoC Updates for v4.4" from Simon Horman:
* ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach helpers
This part of a multi-stage effort by Geert Uytterhoeven to add:
"Clock Domain support to the Clock Pulse Generator (CPG) Module Stop
(MSTP) Clocks driver using the generic PM Domain, to be used on shmobile
SoCs without device power domains (R-Car Gen1 and Gen2, RZ). This allows
to power-manage the module clocks of SoC devices that are part of the
CPG/MSTP Clock Domain using Runtime PM, or for system suspend/resume,
similar to SoCs with device power domains (SH-Mobile and R-Mobile)."* tag 'renesas-soc-for-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach helpers
clk: shmobile: mstp: Consider "zb_clk" suitable for power management
04 Oct, 2015
3 commits
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Pull strscpy string copy function implementation from Chris Metcalf.
Chris sent this during the merge window, but I waffled back and forth on
the pull request, which is why it's going in only now.The new "strscpy()" function is definitely easier to use and more secure
than either strncpy() or strlcpy(), both of which are horrible nasty
interfaces that have serious and irredeemable problems.strncpy() has a useless return value, and doesn't NUL-terminate an
overlong result. To make matters worse, it pads a short result with
zeroes, which is a performance disaster if you have big buffers.strlcpy(), by contrast, is a mis-designed "fix" for strlcpy(), lacking
the insane NUL padding, but having a differently broken return value
which returns the original length of the source string. Which means
that it will read characters past the count from the source buffer, and
you have to trust the source to be properly terminated. It also makes
error handling fragile, since the test for overflow is unnecessarily
subtle.strscpy() avoids both these problems, guaranteeing the NUL termination
(but not excessive padding) if the destination size wasn't zero, and
making the overflow condition very obvious by returning -E2BIG. It also
doesn't read past the size of the source, and can thus be used for
untrusted source data too.So why did I waffle about this for so long?
Every time we introduce a new-and-improved interface, people start doing
these interminable series of trivial conversion patches.And every time that happens, somebody does some silly mistake, and the
conversion patch to the improved interface actually makes things worse.
Because the patch is mindnumbing and trivial, nobody has the attention
span to look at it carefully, and it's usually done over large swatches
of source code which means that not every conversion gets tested.So I'm pulling the strscpy() support because it *is* a better interface.
But I will refuse to pull mindless conversion patches. Use this in
places where it makes sense, but don't do trivial patches to fix things
that aren't actually known to be broken.* 'strscpy' of git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile:
tile: use global strscpy() rather than private copy
string: provide strscpy()
Make asm/word-at-a-time.h available on all architectures -
Pull MIPS updates from Ralf Baechle:
"This week's round of MIPS fixes:
- Fix JZ4740 build
- Fix fallback to GFP_DMA
- FP seccomp in case of ENOSYS
- Fix bootmem panic
- A number of FP and CPS fixes
- Wire up new syscalls
- Make sure BPF assembler objects can properly be disassembled
- Fix BPF assembler code for MIPS I"* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
MIPS: scall: Always run the seccomp syscall filters
MIPS: Octeon: Fix kernel panic on startup from memory corruption
MIPS: Fix R2300 FP context switch handling
MIPS: Fix octeon FP context switch handling
MIPS: BPF: Fix load delay slots.
MIPS: BPF: Do all exports of symbols with FEXPORT().
MIPS: Fix the build on jz4740 after removing the custom gpio.h
MIPS: CPS: #ifdef on CONFIG_MIPS_MT_SMP rather than CONFIG_MIPS_MT
MIPS: CPS: Don't include MT code in non-MT kernels.
MIPS: CPS: Stop dangling delay slot from has_mt.
MIPS: dma-default: Fix 32-bit fall back to GFP_DMA
MIPS: Wire up userfaultfd and membarrier syscalls. -
The MIPS syscall handler code used to return -ENOSYS on invalid
syscalls. Whilst this is expected, it caused problems for seccomp
filters because the said filters never had the change to run since
the code returned -ENOSYS before triggering them. This caused
problems on the chromium testsuite for filters looking for invalid
syscalls. This has now changed and the seccomp filters are always
run even if the syscall is invalid. We return -ENOSYS once we
return from the seccomp filters. Moreover, similar codepaths have
been merged in the process which simplifies somewhat the overall
syscall code.Signed-off-by: Markos Chandras
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11236/
Signed-off-by: Ralf Baechle
03 Oct, 2015
3 commits
-
Pull x86 fixes from Ingo Molnar:
"Fixes all around the map: W+X kernel mapping fix, WCHAN fixes, two
build failure fixes for corner case configs, x32 header fix and a
speling fix"* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/headers/uapi: Fix __BITS_PER_LONG value for x32 builds
x86/mm: Set NX on gap between __ex_table and rodata
x86/kexec: Fix kexec crash in syscall kexec_file_load()
x86/process: Unify 32bit and 64bit implementations of get_wchan()
x86/process: Add proper bound checks in 64bit get_wchan()
x86, efi, kasan: Fix build failure on !KASAN && KMEMCHECK=y kernels
x86/hyperv: Fix the build in the !CONFIG_KEXEC_CORE case
x86/cpufeatures: Correct spelling of the HWP_NOTIFY flag -
Pull EFI fixes from Ingo Molnar:
"Two EFI fixes: one for x86, one for ARM, fixing a boot crash bug that
can trigger under newer EFI firmware"* 'core-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
arm64/efi: Fix boot crash by not padding between EFI_MEMORY_RUNTIME regions
x86/efi: Fix boot crash by mapping EFI memmap entries bottom-up at runtime, instead of top-down -
Pull arm64 fixes from Catalin Marinas:
- Fix for transparent huge page change_protection() logic which was
inadvertently changing a huge pmd page into a pmd table entry.- Function graph tracer panic fix caused by the return_to_handler code
corrupting the multi-regs function return value (composite types).* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64: ftrace: fix function_graph tracer panic
arm64: Fix THP protection change logic