11 Feb, 2016
2 commits
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EOImode1 is only used for the root controller and hence only the root
controller uses the eoimode1 functions for handling interrupts. However,
if the root controller supports EOImode1, then the EOImodeNS bit will be
set for all GICs, enabling EOImode1. This is not what we want and this
causes interrupts on non-root GICs to only be dropped in priority but
never deactivated. Therefore, only set the EOImodeNS bit for the root
controller.Acked-by: Marc Zyngier
Signed-off-by: Jon Hunter
Signed-off-by: Marc Zyngier -
Setting the affinity of an IRQ, it only applicable for the root
interrupt controller and so only populate this operator for the root
controller.Acked-by: Marc Zyngier
Signed-off-by: Jon Hunter
Signed-off-by: Marc Zyngier
04 Feb, 2016
1 commit
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The current ITS driver has a memory leak in its_free_tables(). It
happens on tear down path of the driver when its_probe() call fails.
its_free_tables() should free the exact number of pages that have
been allocated, not just a single page as current code does.This patch records the memory size for each ITS_BASERn at the time of
page allocation and uses the same size information when freeing pages
to fix the issue.Signed-off-by: Shanker Donthineni
Acked-by: Marc Zyngier
Cc: Jason Cooper
Cc: Vikram Sethi
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1454379584-21772-1-git-send-email-shankerd@codeaurora.org
Signed-off-by: Thomas Gleixner
02 Feb, 2016
1 commit
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The Allwinner sunxi specific interrupt controller cannot be compiled
for any architecture except arm:drivers/irqchip/irq-sun4i.c:25:26: fatal error: asm/mach/irq.h: No such file or directory
compilation terminated.It turns out that this header is actually not needed for the driver, so remove
it and allow compilation for other architectures like arm64.Signed-off-by: Andre Przywara
Acked-by: Arnd Bergmann
Cc: linux-arm-kernel@lists.infradead.org
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: Maxime Ripard
Cc: Chen-Yu Tsai
Cc: linux-sunxi@googlegroups.com
Link: http://lkml.kernel.org/r/1454348370-3816-2-git-send-email-andre.przywara@arm.com
Signed-off-by: Thomas Gleixner
01 Feb, 2016
1 commit
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Pull IRQ fixes from Ingo Molnar:
"Mostly irqchip driver fixes, but also an irq core crash fix and a
build fix"* 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
irqchip/mxs: Add missing set_handle_irq()
irqchip/atmel-aic: Fix wrong bit operation for IRQ priority
irqchip/gic-v3-its: Recompute the number of pages on page size change
base: Export platform_msi_domain_[alloc,free]_irqs
of: MSI: Simplify irqdomain lookup
irqdomain: Allow domain lookup with DOMAIN_BUS_WIRED token
irqchip: Fix dependencies for archs w/o HAS_IOMEM
irqchip/s3c24xx: Mark init_eint as __maybe_unused
genirq: Validate action before dereferencing it in handle_irq_event_percpu()
29 Jan, 2016
1 commit
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The rework of the driver missed to move the call to set_handle_irq() into
asm9260_of_init(). As a consequence no interrupt entry point is installed and
no interrupts are deliveredSolution is simple: Install the interrupt entry handler.
Fixes: 7e4ac676ee ("irqchip/mxs: Add Alphascale ASM9260 support")
Signed-off-by: Oleksij Rempel
Cc: kernel@pengutronix.de
Cc: jason@lakedaemon.net
Cc: marc.zyngier@arm.com
Cc: stable@vger.kernel.org
Link: http://lkml.kernel.org/r/1454061473-24957-1-git-send-email-linux@rempel-privat.de
Signed-off-by: Thomas Gleixner
27 Jan, 2016
1 commit
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Atmel AIC has common structure for SMR (Source Mode Register).
bit[6:5] Interrupt source type
bit[2:0] Priority level
Other bits are unused.To update new priority value, bit[2:0] should be cleared first and then
new priority level can be written. However, aic_common_set_priority()
helper clears source type bits instead of priority bits.
This patch fixes wrong mask bit operation.Fixes: b1479ebb7720 "irqchip: atmel-aic: Add atmel AIC/AIC5 drivers"
Signed-off-by: Milo Kim
Acked-by: Boris Brezillon
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: Ludovic Desroches
Cc: Nicholas Ferre
Cc: stable@vger.kernel.org #v3.17+
Link: http://lkml.kernel.org/r/1452669592-3401-2-git-send-email-milo.kim@ti.com
Signed-off-by: Thomas Gleixner
26 Jan, 2016
3 commits
-
When the programming of a GITS_BASERn register fails because of
an unsupported ITS page size, we retry it with a smaller page size.
Unfortunately, we don't recompute the number of allocated ITS pages,
indicating the wrong value computed in the original allocation.A convenient fix is to free the pages we allocated, update the
page size, and restart the allocation. This will ensure that
we always allocate the right amount in the case of a device
table, specially if we have to reduce the allocation order
to stay within the boundaries of the ITS maximum allocation.Reported-and-tested-by: Ma Jun
Signed-off-by: Marc Zyngier
Cc: linux-arm-kernel@lists.infradead.org
Cc: Jason Cooper
Link: http://lkml.kernel.org/r/1453818255-1289-1-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner -
Not every arch has io memory. So, unbreak the build by fixing the
dependencies.Signed-off-by: Richard Weinberger
Cc: user-mode-linux-devel@lists.sourceforge.net
Cc: Jason Cooper
Cc: Marc Zyngier
Link: http://lkml.kernel.org/r/1453760661-1444-19-git-send-email-richard@nod.at
Signed-off-by: Thomas Gleixner -
The init_eint array in the s3c24xx irqchip driver is used by
every individual chip variant, but Kconfig allows building
the driver when they are all disabled, and that leads to
a harmless compile-time warning:drivers/irqchip/irq-s3c24xx.c:608:28: error: 'init_eint' defined but not used [-Werror=unused-variable]
This marks the array as __maybe_unused to avoid the warning.
Signed-off-by: Arnd Bergmann
Acked-by: Marc Zyngier
Cc: linux-arm-kernel@lists.infradead.org
Cc: Jason Cooper
Link: http://lkml.kernel.org/r/1453737499-1960073-1-git-send-email-arnd@arndb.de
Signed-off-by: Thomas Gleixner
25 Jan, 2016
1 commit
-
Pull MIPS updates from Ralf Baechle:
"This is the main pull request for MIPS for 4.5 plus some 4.4 fixes.The executive summary:
- ATH79 platform improvments, use DT bindings for the ATH79 USB PHY.
- Avoid useless rebuilds for zboot.
- jz4780: Add NEMC, BCH and NAND device tree nodes
- Initial support for the MicroChip's DT platform. As all the device
drivers are missing this is still of limited use.
- Some Loongson3 cleanups.
- The unavoidable whitespace polishing.
- Reduce clock skew when synchronizing the CPU cycle counters on CPU
startup.
- Add MIPS R6 fixes.
- Lots of cleanups across arch/mips as fallout from KVM.
- Lots of minor fixes and changes for IEEE 754-2008 support to the
FPU emulator / fp-assist software.
- Minor Ralink, BCM47xx and bcm963xx platform support improvments.
- Support SMP on BCM63168"* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (84 commits)
MIPS: zboot: Add support for serial debug using the PROM
MIPS: zboot: Avoid useless rebuilds
MIPS: BMIPS: Enable ARCH_WANT_OPTIONAL_GPIOLIB
MIPS: bcm63xx: nvram: Remove unused bcm63xx_nvram_get_psi_size() function
MIPS: bcm963xx: Update bcm_tag field image_sequence
MIPS: bcm963xx: Move extended flash address to bcm_tag header file
MIPS: bcm963xx: Move Broadcom BCM963xx image tag data structure
MIPS: bcm63xx: nvram: Use nvram structure definition from header file
MIPS: bcm963xx: Add Broadcom BCM963xx board nvram data structure
MAINTAINERS: Add KVM for MIPS entry
MIPS: KVM: Add missing newline to kvm_err()
MIPS: Move KVM specific opcodes into asm/inst.h
MIPS: KVM: Use cacheops.h definitions
MIPS: Break down cacheops.h definitions
MIPS: Use EXCCODE_ constants with set_except_vector()
MIPS: Update trap codes
MIPS: Move Cause.ExcCode trap codes to mipsregs.h
MIPS: KVM: Make kvm_mips_{init,exit}() static
MIPS: KVM: Refactor added offsetof()s
MIPS: KVM: Convert EXPORT_SYMBOL to _GPL
...
24 Jan, 2016
1 commit
-
This adds support for the interrupt controller present on PIC32 class
devices. It handles all internal and external interrupts. This controller
exists outside of the CPU core and is the arbitrator of all interrupts
(including interrupts from the CPU itself) before they are presented to
the CPU.The following features are supported:
- DT properties for EVIC and for devices/peripherals that use interrupt lines
- Persistent and non-persistent interrupt handling
- irqdomain and generic chip support
- Configuration of external interrupt edge polaritySigned-off-by: Cristian Birsan
Signed-off-by: Joshua Henderson
Acked-by: Thomas Gleixner
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12092/
Signed-off-by: Ralf Baechle
22 Jan, 2016
1 commit
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Pull h8300 updates from Yoshinori Sato:
- Add KGDB support
- zImage fix
- various cleanup* tag 'for-4.5' of git://git.osdn.jp/gitroot/uclinux-h8/linux:
h8300: System call entry enable interrupt.
h8300: show_stack cleanup
h8300: Restraint of warning.
h8300: Add KGDB support.
irqchip: renesas-h8s: Replace ctrl_outw/ctrl_inw with writew/readw
h8300: signal stack fix
h8300: Add LZO compression
h8300: zImage alignment fix
clk: h8300: Remove "sh73a0-" part from compatible value
h8300: zImage alignment fix
21 Jan, 2016
1 commit
-
Pull ARM SoC multiplatform code updates from Arnd Bergmann:
"This branch is the culmination of 5 years of effort to bring the ARMv6
and ARMv7 platforms together such that they can all be enabled and
boot the same kernel. It has been a tremendous amount of cleanup and
refactoring by a huge number of people, and creation of several new
(and major) subsystems to better abstract out all the platform details
in an appropriate manner.The bulk of this branch is a large patchset from Arnd that brings
several of the more minor and older platforms we have closer to
multiplatform support. Among these are MMP, S3C64xx, Orion5x, mv78xx0
and realview Much of this is moving around header files from old mach
directories, but there are also some cleanup patches of debug_ll
(lowlevel debug per-platform options) and other parts.Linus Walleij also has some patchs to clean up the older ARM Realview
platforms by finally introducing DT support, and Rob Herring has some
for ARM Versatile which is now DT-only. Both of these platforms are
now multiplatform.Finally, a couple of patches from Russell for Dove PMU, and a fix from
Valentin Rothberg for Exynos ADC, which were rebased on top of the
series to avoid conflicts"* tag 'armsoc-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (75 commits)
ARM: realview: don't select SMP_ON_UP for UP builds
ARM: s3c: simplify s3c_irqwake_{e,}intallow definition
ARM: s3c64xx: fix pm-debug compilation
iio: exynos-adc: fix irqf_oneshot.cocci warnings
ARM: realview: build realview-dt SMP support only when used
ARM: realview: select apropriate targets
ARM: realview: clean up header files
ARM: realview: make all header files local
ARM: no longer make CPU targets visible separately
ARM: integrator: use explicit core module options
ARM: realview: enable multiplatform
ARM: make default platform work for NOMMU
ARM: debug-ll: move DEBUG_LL_UART_EFM32 to correct Kconfig location
ARM: defconfig: use correct debug_ll settings
ARM: versatile: convert to multi-platform
ARM: versatile: merge mach code into a single file
ARM: versatile: switch to DT only booting and remove legacy code
ARM: versatile: add DT based PCI detection
ARM: pxa: mark ezx structures as __maybe_unused
ARM: pxa: mark raumfeld init functions as __maybe_unused
...
20 Jan, 2016
1 commit
-
Commit 13ae42a3b1c1 ("h8300: Rename ctlr_out/in[bwl] to
raw_read/write[bwl]") changed the function names, but not all callers,
resulting indrivers/irqchip/irq-renesas-h8s.c: In function ‘h8s_disable_irq’:
drivers/irqchip/irq-renesas-h8s.c:43:9: error:
implicit declaration of function ‘ctrl_inw’
drivers/irqchip/irq-renesas-h8s.c:44:2: error:
implicit declaration of function ‘ctrl_outw’Fixes: 13ae42a3b1c1 ("h8300: Rename ctlr_out/in[bwl] to raw_read/write[bwl]")
Cc: Daniel Lezcano
Signed-off-by: Guenter Roeck
12 Jan, 2016
2 commits
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Pull irq updates from Thomas Gleixner:
"The irq department provides:- Support for MSI to wire bridges and a first user of it
- More ACPI support for ARM/GIC
- A new TS-4800 interrupt controller driver
- RCU based free of interrupt descriptors to support the upcoming
Intel VMD technology without introducing a locking nightmare- The usual pile of fixes and updates to drivers and core code"
* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (41 commits)
irqchip/omap-intc: Add support for spurious irq handling
irqchip/zevio: Use irq_data_get_chip_type() helper
irqchip/omap-intc: Remove duplicate setup for IRQ chip type handler
irqchip/ts4800: Add TS-4800 interrupt controller
irqchip/ts4800: Add documentation for TS-4800 interrupt controller
irq/platform-MSI: Increase the maximum MSIs the MSI framework can support
irqchip/gicv2m: Miscellaneous fixes for v2m resources and SPI ranges
irqchip/bcm2836: Make code more readable
irqchip/bcm2836: Tolerate IRQs while no flag is set in ISR
irqchip/bcm2836: Add SMP support for the 2836
irqchip/bcm2836: Fix initialization of the LOCAL_IRQ_CNT timers
irqchip/gic-v2m: acpi: Introducing GICv2m ACPI support
irqchip/gic-v2m: Refactor to prepare for ACPI support
irqdomain: Introduce is_fwnode_irqchip helper
acpi: pci: Setup MSI domain for ACPI based pci devices
genirq/msi: Export functions to allow MSI domains in modules
irqchip/mbigen: Implement the mbigen irq chip operation functions
irqchip/mbigen: Create irq domain for each mbigen device
irqchip/mgigen: Add platform device driver for mbigen device
dt-bindings: Documents the mbigen bindings
... -
…t.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull timer updates - and a leftover fix - from Thomas Gleixner:
"A rather large (commit wise) update from the timer side:- A bulk update to make compile tests work in the clocksource drivers
- An overhaul of the h8300 timers
- Some more Y2038 work
- A few overflow prevention checks in the timekeeping/ntp code
- The usual pile of fixes and improvements to the various
clocksource/clockevent drivers and core code"Also:
"A single fix for the posix-clock poll code which did not make it into
4.4"* 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (84 commits)
clocksource/drivers/acpi_pm: Convert to pr_* macros
clocksource: Make clocksource validation work for all clocksources
timekeeping: Cap adjustments so they don't exceed the maxadj value
ntp: Fix second_overflow's input parameter type to be 64bits
ntp: Change time_reftime to time64_t and utilize 64bit __ktime_get_real_seconds
timekeeping: Provide internal function __ktime_get_real_seconds
clocksource/drivers/h8300: Use ioread / iowrite
clocksource/drivers/h8300: Initializer cleanup.
clocksource/drivers/h8300: Simplify delta handling
clocksource/drivers/h8300: Fix timer not overflow case
clocksource/drivers/h8300: Change to overflow interrupt
clocksource/drivers/lpc32: Correct pr_err() output format
clocksource/drivers/arm_global_timer: Fix suspend resume
clocksource/drivers/pistachio: Fix wrong calculated clocksource read value
clockevents/drivers/arm_global_timer: Use writel_relaxed in gt_compare_set
clocksource/drivers/dw_apb_timer: Inline apbt_readl and apbt_writel
clocksource/drivers/dw_apb_timer: Use {readl|writel}_relaxed in critical path
clocksource/drivers/dw_apb_timer: Fix apbt_readl return types
clocksource/drivers/tango-xtal: Replace code by clocksource_mmio_init
clocksource/drivers/h8300: Increase the compilation test coverage
...* 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
posix-clock: Fix return code on the poll method's error path
06 Jan, 2016
1 commit
-
Under some conditions, irq sorting procedure used by INTC can go wrong
resulting in a spurious irq getting reported.If this condition is not handled, it results in endless stream of:
unexpected IRQ trap at vector 00
messages from ack_bad_irq()
Handle the spurious interrupt condition in omap-intc driver to prevent this.
Measurements using kernel function profiler on AM335x EVM running at 720MHz
show that after this patch omap_intc_handle_irq() takes about 37.4us against
34us before this patch.Signed-off-by: Sekhar Nori
Acked-by: Tony Lindgren
Cc: John Ogness
Cc: Felipe Balbi
Cc: Jason Cooper
Cc: Marc Zyngier
Link: http://lkml.kernel.org/r/9c78a6db02ac55f7af7371b417b6e414d2c3095b.1450188128.git.nsekhar@ti.com
Cc: stable@vger.kernel.org
Signed-off-by: Thomas Gleixner
31 Dec, 2015
1 commit
-
Use irq_data_get_chip_type() instead of container_of().
Signed-off-by: Geliang Tang
Cc: Jason Cooper
Cc: Marc Zyngier
Link: http://lkml.kernel.org/r/4cc3a3a7a74c7a1894892a85aa7eabbd1534fe96.1451484758.git.geliangtang@163.com
Signed-off-by: Thomas Gleixner
29 Dec, 2015
9 commits
-
Some OMAP interrupt controllers use generic level detection, so
handle_level_irq() is used as the chip type handler.
Allocated IRQ chip type handler doesn't need to set it again because
irq_alloc_domain_generic_chips() has already registered it.Tested with BeagleBoneBlack Rev C.
Signed-off-by: Milo Kim
Cc: Tony Lindgren
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: linux-omap@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Link: http://lkml.kernel.org/r/1450687994-12580-1-git-send-email-milo.kim@ti.com
Signed-off-by: Thomas Gleixner -
This commit adds support for the TS-4800 interrupt controller. This
controller is instantiated in a companion FPGA, and multiplex interrupts
for other FPGA IPs.As this component is external to the SoC, the SoC might need to reserve
pins, so this controller is implemented as a platform driver and doesn't
use the IRQCHIP_DECLARE construct.Signed-off-by: Damien Riegel
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Ian Campbell
Cc: Kumar Gala
Cc: kernel@savoirfairelinux.com
Link: http://lkml.kernel.org/r/1450728683-31416-2-git-send-email-damien.riegel@savoirfairelinux.com
Signed-off-by: Thomas Gleixner -
This patch contain fixes for v2m resources and SPI ranges:
* Fix off-by-one error when set up v2m resource end range in
gicv2m_acpi_init().* Fix the off-by-one print error for SPI range.
* Use %pR to properly print resource range information.
Both ACPI and DT should now print:
GICv2m: range[mem 0xe1180000-0xe1180fff], SPI[64:319]
Suggested-by: Bjorn Helgaas
Signed-off-by: Suravee Suthikulpanit
Cc: Lorenzo Pieralisi
Cc: Will Deacon
Cc: Catalin Marinas
Cc:
Cc:
Cc:
Cc:
Cc:
Cc:
Cc:
Cc:
Link: http://lkml.kernel.org/r/1450830263-28914-1-git-send-email-Suravee.Suthikulpanit@amd.com
Signed-off-by: Thomas Gleixner -
Avoid using hardcoded magics. We have a #define for this number.
No functional changes.Signed-off-by: Andrea Merello
Reviewed-by: Eric Anholt
Signed-off-by: Eric Anholt
Cc: linux-arm-kernel@lists.infradead.org
Cc: Stephen Warren
Cc: Lee Jones
Cc: Florian Fainelli
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: linux-rpi-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1451166444-11044-5-git-send-email-eric@anholt.net
Signed-off-by: Thomas Gleixner -
On my RPi2 I got a lot of:
unexpected IRQ trap at vector 00This happens because bcm2836_arm_irqchip_handle_irq() is sometimes
invoked even if the ISR is clear, and this case is not handled.This patch explicitly handle this case, fixing the kernel complaints
about the bad IRQ lookup.Signed-off-by: Andrea Merello
Reviewed-by: Eric Anholt
Signed-off-by: Eric Anholt
Cc: linux-arm-kernel@lists.infradead.org
Cc: Stephen Warren
Cc: Lee Jones
Cc: Florian Fainelli
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: linux-rpi-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1451166444-11044-4-git-send-email-eric@anholt.net
Signed-off-by: Thomas Gleixner -
The firmware sets the secondaries spinning waiting for a non-NULL
value to show up in the last IPI mailbox.The original SMP port from the downstream tree was done by Andrea, and
Eric cleaned it up/rewrote it a few times from there.Signed-off-by: Andrea Merello
Signed-off-by: Eric Anholt
Cc: linux-arm-kernel@lists.infradead.org
Cc: Stephen Warren
Cc: Lee Jones
Cc: Florian Fainelli
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: linux-rpi-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1451166444-11044-3-git-send-email-eric@anholt.net
Signed-off-by: Thomas Gleixner -
The irqchip's register area includes the the setup for the timer's
scaling factors, and for the platform we want a fixed configuration of
these registers.Signed-off-by: Eric Anholt
Cc: linux-arm-kernel@lists.infradead.org
Cc: Stephen Warren
Cc: Lee Jones
Cc: Florian Fainelli
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: linux-rpi-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1451166444-11044-2-git-send-email-eric@anholt.net
Signed-off-by: Thomas Gleixner -
Pull irqchip core changes for v4.5 from Jason Cooper:
- renesas-intc-irqpin: Remove platform code, improve clock handling
- sunxi-nmi: Extend NMI support to include A80
-
…/maz/arm-platforms into irq/core
Pull another round of GIC changes from Marc:
ACPI support for GIV-v2m
24 Dec, 2015
1 commit
21 Dec, 2015
3 commits
-
This patch introduces gicv2m_acpi_init(), which uses information
in MADT GIC MSI frames structure to initialize GICv2m driver.
It also exposes gicv2m_init() function, which simplifies callers
to a single GICv2m init function.Reviewed-by: Marc Zyngier
Tested-by: Duc Dang
Acked-by: Rafael J. Wysocki
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Hanjun Guo
Signed-off-by: Marc Zyngier -
This patch replaces the struct device_node with struct fwnode_handle
since this structure is common between DT and ACPI.It also refactors gicv2m_init_one() to prepare for ACPI support.
The only functional change is removing the node name from pr_info.Reviewed-by: Marc Zyngier
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Marc Zyngier -
Since there will be several places checking if fwnode.type
is equal FWNODE_IRQCHIP, this patch adds a convenient function
for this purpose.Acked-by: Marc Zyngier
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Marc Zyngier
19 Dec, 2015
1 commit
-
…arm-platforms into irq/core
Pull the GIC related updates from Marc Zyngier:
"Not a lot this time (what a relief!), but an interesting series from
Linus Walleij coming out of his work converting the ARM RealView
platforms to DT, and a couple of mundane fixes."
18 Dec, 2015
4 commits
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Add the interrupt controller chip operation functions of mbigen chip.
Signed-off-by: Ma Jun
Reviewed-by: Marc Zyngier
Signed-off-by: Marc Zyngier -
For peripheral devices which connect to mbigen,mbigen is a interrupt
controller. So, we create irq domain for each mbigen device and add
mbigen irq domain into irq hierarchy structure.Signed-off-by: Ma Jun
Reviewed-by: Marc Zyngier
Signed-off-by: Marc Zyngier -
Mbigen means Message Based Interrupt Generator(MBIGEN).
Its a kind of interrupt controller that collects
the interrupts from external devices and generate msi interrupt.
Mbigen is applied to reduce the number of wire connected interrupts.As the peripherals increasing, the interrupts lines needed is
increasing much, especially on the Arm64 server SOC.Therefore, the interrupt pin in GIC is not enough to cover so
many peripherals.Mbigen is designed to fix this problem.
Mbigen chip locates in ITS or outside of ITS.
Mbigen chip hardware structure shows as below:
mbigen chip
|---------------------|-------------------|
mgn_node0 mgn_node1 mgn_node2
| |-------| |-------|------|
dev1 dev1 dev2 dev1 dev3 dev4Each mbigen chip contains several mbigen nodes.
External devices can connect to mbigen node through wire connecting way.
Because a mbigen node only can support 128 interrupt maximum, depends
on the interrupt lines number of devices, a device can connects to one
more mbigen nodes.Also, several different devices can connect to a same mbigen node.
When devices triggered interrupt,mbigen chip detects and collects
the interrupts and generates the MBI interrupts by writing the ITS
Translator register.To simplify mbigen driver,I used a new conception--mbigen device.
Each mbigen device is initialized as a platform device.Mbigen device presents the parts(register, pin definition etc.) in
mbigen chip corresponding to a peripheral device.So from software view, the structure likes below
mbigen chip
|---------------------|-----------------|
mbigen device1 mbigen device2 mbigen device3
| | |
dev1 dev2 dev3Reviewed-by: Marc Zyngier
Signed-off-by: Ma Jun
Signed-off-by: Marc Zyngier -
There is currently a hack in the GIC driver making it possible
to pass the number of GIC instances from the platform-specific
include files and thus override the variable MAX_GIC_NR.With multiplatform deployments, this will not work as we need
to get rid of the platform-specific include files.It turns out that this feature is only used by the RealView
platform which has a cascaded GIC. So move the configuration
to Kconfig and bump to 2 instances if we're building for the
RealView. The include file hacks can then be removed.Tested on the ARM PB11MPCore with its cascaded GIC.
Suggested-by: Arnd Bergmann
Signed-off-by: Linus Walleij
Signed-off-by: Marc Zyngier
16 Dec, 2015
3 commits
-
The GIC has no such thing as interrupt 1020: the last valid ID is
1019, and the range 1020-1023 is reserved - 1023 indicating that
no interrupt is pending. So let's make sure we don't try to handle
this ID.This bug has been in since the initial GIC code was introduced in
8ad68bbf7a06 ("[ARM] Add support for ARM RealView board").Reported-by: Eric Auger
Cc: Catalin Marinas
Signed-off-by: Marc Zyngier -
On the error path, the v2m drivers drops the refcount on the parent
node instead of doing it on the node that generated the error.
Humph...Reported-by: Thomas Petazzoni
Signed-off-by: Marc Zyngier -
Instead of having the irqchip being a static struct, make it part
of the per-instance data so we can assign it a dynamic name. This
has the usable side effect of displaying the GIC with an instance
number as GIC0, GIC1 ... GICn in /proc/interrupts, which is helpful
when debugging cascaded GICs, such as on the ARM PB11MPCore.Cc: Thomas Gleixner
Cc: Jason Cooper
Signed-off-by: Linus Walleij
Signed-off-by: Marc Zyngier