21 Oct, 2022
1 commit
-
In order to fix "MIPI DSI no display after suspend/resume". The LVDS pixel
and phy clocks must be initialized before the MIPI tx_esacpe and rx_escape
clocks. LVDS phy, LVDS pixel, tx_escape, and rx_esacpe are all on the same
MSLICE. They all share the same clock parent. So, setting the parent source
or rate affects all of these clocks. In the LVDS use case the MIPI tx_escape
and rx_escape are not saved and restored. So, LVDS works for either clock
initialization order. For MIPI case, LVDS must be initialized first.This patch can be squashed into "LF-7054-1: clk: imx: clk-imx8qxp: Add LVDS
bypass clocks" which should not have changed the initialization order.Signed-off-by: Oliver F. Brown
Reviewed-by: Liu Ying
13 Oct, 2022
1 commit
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XBAR_DIVBUS and AD_SLOW should set parent to XBAR_AD_DIVPLAT and
XBAR_DIVBUS respectively, not the NIC_AD. otherwise we will get
wrong clock rate.Signed-off-by: Ye Li
Reviewed-by: Jacky Bai
11 Oct, 2022
1 commit
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Keep sys ctr clock always on to make sure its register
can be accessed.Signed-off-by: Jacky Bai
Reviewed-by: Peng Fan
10 Oct, 2022
1 commit
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Per Reference Mannual System Clocks Table,
LPIT1 and TPM1 sources from bus_aon_root
LPIT2 and TPM3 sources from bus_wakeup_rootSo update driver to reflect that.
Reviewed-by: Jacky Bai
Signed-off-by: Peng Fan
09 Oct, 2022
2 commits
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When doing linux system suspend stress test after system sleep
enabled, sometimes, system will stuck. after some debug & narrow
down, it seems keep HSIO root clock ON can workaround this issue.As the NICMIX power down can NOT be skipped for now, so it is hard
to check if this issue is related to the NICMIX power down.so keep the HSIO root clock enabled as a temp workaround before we
have find out the root cause of the issue.Signed-off-by: Jacky Bai
Reviewed-by: Peng Fan -
for the PLL used on i.MX9, the VCO frequency must be in the range
of 2.5GHz - 5GHz, so update the PLL setting to meet this requirement.Signed-off-by: Jacky Bai
Reviewed-by: Ye Li
01 Oct, 2022
1 commit
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For iMX8QXP and iMX8QM, add bypass clocks and register some of the LVDS clocks
with imx_clk_scu2 as the parent needs to explicitly set.Signed-off-by: Ranjani Vaidyanathan
Signed-off-by: Oliver F. Brown
30 Sep, 2022
1 commit
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Correct IMX93_CLK_FLEXSPI1_GATE ccgr setting.
Signed-off-by: Haibo Chen
Reviewed-by: Han Xu
27 Sep, 2022
1 commit
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This is the 5.15.70 stable release
* tag 'v5.15.70': (2444 commits)
Linux 5.15.70
ALSA: hda/sigmatel: Fix unused variable warning for beep power change
cgroup: Add missing cpus_read_lock() to cgroup_attach_task_all()
...Signed-off-by: Jason Liu
Conflicts:
arch/arm/boot/dts/imx6ul.dtsi
arch/arm/mm/mmu.c
arch/arm64/boot/dts/freescale/imx8mp-evk.dts
drivers/gpu/drm/imx/dcss/dcss-kms.c
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg.c
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg.h
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c
drivers/soc/fsl/Kconfig
drivers/soc/imx/gpcv2.c
drivers/usb/dwc3/host.c
net/dsa/slave.c
sound/soc/fsl/imx-card.c
08 Sep, 2022
7 commits
-
[ Upstream commit 13b5cf8d6a0d4a5d289e1ed046cadc63b416db85 ]
Some log messages lacks the final newline. So add them.
Fixes: 93d2725affd6 ("clk: bcm: rpi: Discover the firmware clocks")
Signed-off-by: Stefan Wahren
Link: https://lore.kernel.org/r/20220713154953.3336-3-stefan.wahren@i2se.com
Acked-by: Florian Fainelli
Reviewed-by: Ivan T. Ivanov
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
[ Upstream commit bc163555603e4ae9c817675ad80d618a4cdbfa2d ]
The while loop in raspberrypi_discover_clocks() relies on the assumption
that the id of the last clock element is zero. Because this data comes
from the Videocore firmware and it doesn't guarantuee such a behavior
this could lead to out-of-bounds access. So fix this by providing
a sentinel element.Fixes: 93d2725affd6 ("clk: bcm: rpi: Discover the firmware clocks")
Link: https://github.com/raspberrypi/firmware/issues/1688
Suggested-by: Phil Elwell
Signed-off-by: Stefan Wahren
Link: https://lore.kernel.org/r/20220713154953.3336-2-stefan.wahren@i2se.com
Acked-by: Florian Fainelli
Reviewed-by: Ivan T. Ivanov
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
[ Upstream commit b7fa6242f3e035308a76284560e4f918dad9b017 ]
We should have 'n', then 'size', not the opposite.
This is harmless because the 2 values are just multiplied, but having
the correct order silence a (unpublished yet) smatch warning.Signed-off-by: Christophe JAILLET
Link: https://lore.kernel.org/r/49d726d11964ca0e3757bdb5659e3b3eaa1572b5.1653081643.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
[ Upstream commit 35f73cca1cecda0c1f8bb7d8be4ce5cd2d46ae8c ]
The function raspberrypi_fw_get_rate (e.g. used for the recalc_rate
hook) can fail to get the clock rate from the firmware. In this case
we cannot return a signed error value, which would be casted to
unsigned long. Fix this by returning 0 instead.Signed-off-by: Stefan Wahren
Link: https://lore.kernel.org/r/20220625083643.4012-1-stefan.wahren@i2se.com
Fixes: 4e85e535e6cc ("clk: bcm283x: add driver interfacing with Raspberry Pi's firmware")
Acked-by: Florian Fainelli
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
[ Upstream commit 4b592061f7b3971c70e8b72fc42aaead47c24701 ]
In the original commit 9a34b45397e5 ("clk: Add support for runtime PM"),
the commit message mentioned that pm_runtime_put_sync() would be done
at the end of clk_core_unprepare(). This mirrors the operations in
clk_core_prepare() in the opposite order.However, the actual code that was added wasn't in the order the commit
message described. Move clk_pm_runtime_put() to the end of
clk_core_unprepare() so that it is in the correct order.Fixes: 9a34b45397e5 ("clk: Add support for runtime PM")
Signed-off-by: Chen-Yu Tsai
Reviewed-by: Nícolas F. R. A. Prado
Link: https://lore.kernel.org/r/20220822081424.1310926-3-wenst@chromium.org
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
[ Upstream commit abb5f3f4b1f5f0ad50eb067a00051d3587dec9fb ]
This reverts commit 35b0fac808b95eea1212f8860baf6ad25b88b087. Alexander
reports that it causes boot failures on i.MX8M Plus based boards
(specifically imx8mp-tqma8mpql-mba8mpxl.dts).Reported-by: Alexander Stein
Cc: Chen-Yu Tsai
Fixes: 35b0fac808b9 ("clk: core: Honor CLK_OPS_PARENT_ENABLE for clk gate ops")
Link: https://lore.kernel.org/r/12115951.O9o76ZdvQC@steina-w
Signed-off-by: Stephen Boyd
Link: https://lore.kernel.org/r/20220831175326.2523912-1-sboyd@kernel.org
Signed-off-by: Sasha Levin -
[ Upstream commit 35b0fac808b95eea1212f8860baf6ad25b88b087 ]
In the previous commits that added CLK_OPS_PARENT_ENABLE, support for
this flag was only added to rate change operations (rate setting and
reparent) and disabling unused subtree. It was not added to the
clock gate related operations. Any hardware driver that needs it for
these operations will either see bogus results, or worse, hang.This has been seen on MT8192 and MT8195, where the imp_ii2_* clk
drivers set this, but dumping debugfs clk_summary would cause it
to hang.Fixes: fc8726a2c021 ("clk: core: support clocks which requires parents enable (part 2)")
Fixes: a4b3518d146f ("clk: core: support clocks which requires parents enable (part 1)")
Signed-off-by: Chen-Yu Tsai
Reviewed-by: Nícolas F. R. A. Prado
Tested-by: Nícolas F. R. A. Prado
Link: https://lore.kernel.org/r/20220822081424.1310926-2-wenst@chromium.org
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin
25 Aug, 2022
4 commits
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[ Upstream commit 94bed9bb05c7850ff5d80b87cc29004901f37956 ]
After merging lucid and trion pll functions in commit 0b01489475c6
("clk: qcom: clk-alpha-pll: same regs and ops for trion and lucid")
the function clk_trion_pll_configure() is left with an old description
header, which results in a W=2 compile time warning, fix it.Acked-by: Stephen Boyd
Reviewed-by: Vinod Koul
Signed-off-by: Vladimir Zapolskiy
Signed-off-by: Bjorn Andersson
Link: https://lore.kernel.org/r/20220701062711.2757855-1-vladimir.zapolskiy@linaro.org
Signed-off-by: Sasha Levin -
[ Upstream commit 1bf7305e79aab095196131bdc87a97796e0e3fac ]
Once the usb sleep clocks are disabled, clock framework is trying to
disable the sleep clock source also.However, it seems that it cannot be disabled and trying to do so produces:
[ 245.436390] ------------[ cut here ]------------
[ 245.441233] gcc_sleep_clk_src status stuck at 'on'
[ 245.441254] WARNING: CPU: 2 PID: 223 at clk_branch_wait+0x130/0x140
[ 245.450435] Modules linked in: xhci_plat_hcd xhci_hcd dwc3 dwc3_qcom leds_gpio
[ 245.456601] CPU: 2 PID: 223 Comm: sh Not tainted 5.18.0-rc4 #215
[ 245.463889] Hardware name: Xiaomi AX9000 (DT)
[ 245.470050] pstate: 204000c5 (nzCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[ 245.474307] pc : clk_branch_wait+0x130/0x140
[ 245.481073] lr : clk_branch_wait+0x130/0x140
[ 245.485588] sp : ffffffc009f2bad0
[ 245.489838] x29: ffffffc009f2bad0 x28: ffffff8003e6c800 x27: 0000000000000000
[ 245.493057] x26: 0000000000000000 x25: 0000000000000000 x24: ffffff800226ef20
[ 245.500175] x23: ffffffc0089ff550 x22: 0000000000000000 x21: ffffffc008476ad0
[ 245.507294] x20: 0000000000000000 x19: ffffffc00965ac70 x18: fffffffffffc51a7
[ 245.514413] x17: 68702e3030303837 x16: 3a6d726f6674616c x15: ffffffc089f2b777
[ 245.521531] x14: ffffffc0095c9d18 x13: 0000000000000129 x12: 0000000000000129
[ 245.528649] x11: 00000000ffffffea x10: ffffffc009621d18 x9 : 0000000000000001
[ 245.535767] x8 : 0000000000000001 x7 : 0000000000017fe8 x6 : 0000000000000001
[ 245.542885] x5 : ffffff803fdca6d8 x4 : 0000000000000000 x3 : 0000000000000027
[ 245.550002] x2 : 0000000000000027 x1 : 0000000000000023 x0 : 0000000000000026
[ 245.557122] Call trace:
[ 245.564229] clk_branch_wait+0x130/0x140
[ 245.566490] clk_branch2_disable+0x2c/0x40
[ 245.570656] clk_core_disable+0x60/0xb0
[ 245.574561] clk_core_disable+0x68/0xb0
[ 245.578293] clk_disable+0x30/0x50
[ 245.582113] dwc3_qcom_remove+0x60/0xc0 [dwc3_qcom]
[ 245.585588] platform_remove+0x28/0x60
[ 245.590361] device_remove+0x4c/0x80
[ 245.594179] device_release_driver_internal+0x1dc/0x230
[ 245.597914] device_driver_detach+0x18/0x30
[ 245.602861] unbind_store+0xec/0x110
[ 245.607027] drv_attr_store+0x24/0x40
[ 245.610847] sysfs_kf_write+0x44/0x60
[ 245.614405] kernfs_fop_write_iter+0x128/0x1c0
[ 245.618052] new_sync_write+0xc0/0x130
[ 245.622391] vfs_write+0x1d4/0x2a0
[ 245.626123] ksys_write+0x58/0xe0
[ 245.629508] __arm64_sys_write+0x1c/0x30
[ 245.632895] invoke_syscall.constprop.0+0x5c/0x110
[ 245.636890] do_el0_svc+0xa0/0x150
[ 245.641488] el0_svc+0x18/0x60
[ 245.644872] el0t_64_sync_handler+0xa4/0x130
[ 245.647914] el0t_64_sync+0x174/0x178
[ 245.652340] ---[ end trace 0000000000000000 ]---So, add CLK_IS_CRITICAL flag to the clock so that the kernel won't try
to disable the sleep clock.Signed-off-by: Robert Marko
Signed-off-by: Bjorn Andersson
Link: https://lore.kernel.org/r/20220515210048.483898-10-robimarko@gmail.com
Signed-off-by: Sasha Levin -
[ Upstream commit 255584b138343d4a28c6d25bd82d04b09460d672 ]
With the addition of clock-output-names, we can now unify the internal
clock naming for omap4 and 5 to follow the other TI SoCs.We are still using legacy clkctrl names for omap4 and 5 based on the clock
manager name which is wrong. Instead, we want to use the clkctrl clock
based naming.We must now also drop the legacy TI_CLK_CLKCTRL_COMPAT quirk for the
clkctrl clock.This change will allow further devicetree warning cleanup as already
done for am3/4 and dra7.Cc: linux-clk@vger.kernel.org
Cc: Stephen Boyd
Cc: Tero Kristo
Signed-off-by: Tony Lindgren
Link: https://lore.kernel.org/r/20220615064306.22254-1-tony@atomide.com
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
Some of the PCCs on i.MX8ULP have a sw_rst bit to control
the peripheral reset through SW method. For peripherals like GPU
that need sync reset, some delay is necessary befere & after release
the reset to make sure the HW is reset into known status. So add
some delay before & after release reset.Signed-off-by: Jacky Bai
Reviewed-by: Peng Fan
17 Aug, 2022
16 commits
-
[ Upstream commit 2bc308ebc453ba22f3f120f777b9ac48f973ee80 ]
Adding a new item to this frequency table I see the existing indentation is
incorrect.Fixes: 1664014e4679 ("clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller")
Signed-off-by: Bryan O'Donoghue
Reviewed-by: Konrad Dybcio
Signed-off-by: Bjorn Andersson
Link: https://lore.kernel.org/r/20220712125922.3461675-2-bryan.odonoghue@linaro.org
Signed-off-by: Sasha Levin -
[ Upstream commit d0696770cef35a1fd16ea2167e2198c18aa6fbfe ]
Sometimes calculation of d value may result in 0 because of the
rounding after integer division. This causes the following error:[ 113.969689] camss_gp1_clk_src: rcg didn't update its configuration.
[ 113.969754] WARNING: CPU: 3 PID: 35 at drivers/clk/qcom/clk-rcg2.c:122 update_config+0xc8/0xdcMake sure that D value is never zero.
Fixes: 7f891faf596e ("clk: qcom: clk-rcg2: Add support for duty-cycle for RCG")
Signed-off-by: Nikita Travkin
Reviewed-by: Stephen Boyd
Signed-off-by: Bjorn Andersson
Link: https://lore.kernel.org/r/20220612145955.385787-3-nikita@trvn.ru
Signed-off-by: Sasha Levin -
[ Upstream commit bdafb609c3bb848d710ad9cd4debd2ee9d6a4049 ]
In cases when MND is not enabled (e.g. when only Half Integer Divider is
used), setting D registers makes no effect.Fail instead of making ineffective write.
Fixes: 7f891faf596e ("clk: qcom: clk-rcg2: Add support for duty-cycle for RCG")
Signed-off-by: Nikita Travkin
Reviewed-by: Stephen Boyd
Signed-off-by: Bjorn Andersson
Link: https://lore.kernel.org/r/20220612145955.385787-2-nikita@trvn.ru
Signed-off-by: Sasha Levin -
[ Upstream commit f8acf01a6a4f84baf05181e24bd48def4ba23f5b ]
On SM8250 two found VFE GDSC power domains shall not be operated, if
titan top is turned off, thus the former power domains will be set as
subdomains by a GDSC registration routine.Fixes: 5d66ca79b58c ("clk: qcom: Add camera clock controller driver for SM8250")
Signed-off-by: Vladimir Zapolskiy
Reviewed-by: Robert Foss
Signed-off-by: Bjorn Andersson
Link: https://lore.kernel.org/r/20220519214133.1728979-3-vladimir.zapolskiy@linaro.org
Signed-off-by: Sasha Levin -
[ Upstream commit 103dd2338bbff567bce7acd00fc5a09c806b38ec ]
On SDM845 two found VFE GDSC power domains shall not be operated, if
titan top is turned off, thus the former power domains will be set as
subdomains by a GDSC registration routine.Fixes: 78412c262004 ("clk: qcom: Add camera clock controller driver for SDM845")
Signed-off-by: Vladimir Zapolskiy
Reviewed-by: Robert Foss
Signed-off-by: Bjorn Andersson
Link: https://lore.kernel.org/r/20220519214133.1728979-2-vladimir.zapolskiy@linaro.org
Signed-off-by: Sasha Levin -
[ Upstream commit 2bd357e698207e2e65db03007e4be65bf9d6a7b3 ]
Currently, attempting to enable the UBI clocks will cause the stuck at
off warning to be printed and clk_enable will fail.[ 14.936694] gcc_ubi1_ahb_clk status stuck at 'off'
Downstream 5.4 QCA kernel has fixed this by seting the BRANCH_HALT_DELAY
flag on UBI clocks, so lets do the same.Fixes: 5736294aef83 ("clk: qcom: ipq8074: add NSS clocks")
Signed-off-by: Robert Marko
Signed-off-by: Bjorn Andersson
Link: https://lore.kernel.org/r/20220515210048.483898-6-robimarko@gmail.com
Signed-off-by: Sasha Levin -
[ Upstream commit 0e9e61a2815b5cd34f1b495b2d72e8127ce9b794 ]
NSS port 5 and 6 frequency tables are currently broken and are causing a
wide ranges of issue like 1G not working at all on port 6 or port 5 being
clocked with 312 instead of 125 MHz as UNIPHY1 gets selected.So, update the frequency tables with the ones from the downstream QCA 5.4
based kernel which has already fixed this.Fixes: 7117a51ed303 ("clk: qcom: ipq8074: add NSS ethernet port clocks")
Signed-off-by: Robert Marko
Signed-off-by: Bjorn Andersson
Link: https://lore.kernel.org/r/20220515210048.483898-3-robimarko@gmail.com
Signed-off-by: Sasha Levin -
[ Upstream commit 3401ea2856ef84f39b75f0dc5ebcaeda81cb90ec ]
UBI32 Huayra PLL fails to lock in 5 us in some SoC silicon and thus it
will cause the wait_for_pll() to timeout and thus return the error
indicating that the PLL failed to lock.This is bug in Huayra PLL HW for which SW workaround
is to set bit 26 of TEST_CTL register.This is ported from the QCA 5.4 based downstream kernel.
Fixes: b8e7e519625f ("clk: qcom: ipq8074: add remaining PLL’s")
Signed-off-by: Robert Marko
Signed-off-by: Bjorn Andersson
Link: https://lore.kernel.org/r/20220515210048.483898-2-robimarko@gmail.com
Signed-off-by: Sasha Levin -
[ Upstream commit ca41ec1b30434636c56c5600b24a8d964d359d9c ]
Like in IPQ6018 the NSS related Alpha PLL-s require initial configuration
to work.So, obtain the regmap that is required for the Alpha PLL configuration
and thus utilize the qcom_cc_really_probe() as we already have the regmap.
Then utilize the Alpha PLL configs from the downstream QCA 5.4 based
kernel to configure them.This fixes the UBI32 and NSS crypto PLL-s failing to get enabled by the
kernel.Fixes: b8e7e519625f ("clk: qcom: ipq8074: add remaining PLL’s")
Signed-off-by: Robert Marko
Signed-off-by: Bjorn Andersson
Link: https://lore.kernel.org/r/20220515210048.483898-1-robimarko@gmail.com
Signed-off-by: Sasha Levin -
[ Upstream commit 05eed0990927aa9634682fec58660e30f7b7ae30 ]
Qcom docs indciate the following peripherals operating from System NOC
MM not from System NOC clocks.- MDP
- VFE
- JPEGe
- VenusSwitch over the relevant parent pointers.
Fixes: 1664014e4679 ("clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller")
Signed-off-by: Bryan O'Donoghue
Signed-off-by: Bjorn Andersson
Link: https://lore.kernel.org/r/20220504163835.40130-5-bryan.odonoghue@linaro.org
Signed-off-by: Sasha Levin -
[ Upstream commit dd363e2f7196278e7a30f509a0e8a841cb763b14 ]
The msm8939 has an additional higher operating point for the multi-media
peripherals. The higher throughput MM componets operate off of the
system-mm noc not the system noc.system_mm_noc_bfdcd_clk_src is the source clock for the higher frequency
capable system noc mm.Maximum frequency for the MM SNOC is 400 MHz.
Fixes: 1664014e4679 ("clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller")
Signed-off-by: Bryan O'Donoghue
Signed-off-by: Bjorn Andersson
Link: https://lore.kernel.org/r/20220504163835.40130-4-bryan.odonoghue@linaro.org
Signed-off-by: Sasha Levin -
[ Upstream commit 63d42708320d6d2ca9ed505123d50ff4a542c36f ]
Reviewing qcom docs for the 8939 we can see the command rcgr is pointing to
the wrong address. bimc_ddr_clk_src_rcgr is @ 0x01832024 not 0x01832004.Fixes: 1664014e4679 ("clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller")
Signed-off-by: Bryan O'Donoghue
Signed-off-by: Bjorn Andersson
Link: https://lore.kernel.org/r/20220504163835.40130-3-bryan.odonoghue@linaro.org
Signed-off-by: Sasha Levin -
[ Upstream commit df83d2c9e72910416f650ade1e07cc314ff02731 ]
Unlock spinlock after the mux switch is completed to prevent any corner
case of mux request while the switch still needs to be done.Fixes: 4d7dc77babfe ("clk: qcom: Add support for Krait clocks")
Signed-off-by: Ansuel Smith
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Bjorn Andersson
Link: https://lore.kernel.org/r/20220430054458.31321-3-ansuelsmth@gmail.com
Signed-off-by: Sasha Levin -
[ Upstream commit c4f40351901a10cd662ac2c081396d8fb04f584d ]
Access to I/O of SM8250 camera clock controller IP depends on enabled
GCC_CAMERA_AHB_CLK clock supplied by global clock controller, the latter
one is inited on subsys level, so, to satisfy the dependency, it would
make sense to deprive the init level of camcc-sm8250 driver.If both drivers are compiled as built-in, there is a change that a board
won't boot up due to a race, which happens on the same init level.Fixes: 5d66ca79b58c ("clk: qcom: Add camera clock controller driver for SM8250")
Signed-off-by: Vladimir Zapolskiy
Reviewed-by: Bryan O'Donoghue
Tested-by: Bryan O'Donoghue
Signed-off-by: Bjorn Andersson
Link: https://lore.kernel.org/r/20220518103554.949511-1-vladimir.zapolskiy@linaro.org
Signed-off-by: Sasha Levin -
[ Upstream commit edabcf71d100fd433a0fc2d0c97057c446c33b2a ]
Original assert/deassert bit is BIT(0), but it's more resonable to modify
them to BIT(id % 32) which is based on id.This patch will not influence any previous driver because the reset is
only used for thermal. The id (MT8183_INFRACFG_AO_THERM_SW_RST) is 0.Fixes: 64ebb57a3df6 ("clk: reset: Modify reset-controller driver")
Signed-off-by: Rex-BC Chen
Reviewed-by: Chen-Yu Tsai
Reviewed-by: AngeloGioacchino Del Regno
Reviewed-by: Nícolas F. R. A. Prado
Tested-by: Nícolas F. R. A. Prado
Link: https://lore.kernel.org/r/20220523093346.28493-3-rex-bc.chen@mediatek.com
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
[ Upstream commit 2dee50ab9e72a3cae75b65e5934c8dd3e9bf01bc ]
There are two UART clock groups, each having a mux to select its
upstream clock source. The register/bit definitions for accessing these
two muxes appear to have been reversed since introduction. Correct them
so as to match the hardware manual.Fixes: 4c3d88526eba ("clk: renesas: Renesas R9A06G032 clock driver")
Signed-off-by: Ralph Siemsen
Reviewed-by: Phil Edworthy
Link: https://lore.kernel.org/r/20220518182527.1693156-1-ralph.siemsen@linaro.org
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Sasha Levin
12 Aug, 2022
1 commit
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This reverts commit c5559147766c6de7ded2db62b8aeaa579c66750b.
with original way, we can keep the gate on for usb wakeup, and AXI
hsio clock off in low power mode.Reviewed-by: Jacky Bai
Signed-off-by: Li Jun
02 Aug, 2022
3 commits
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This is a workaround to make
- usb resume when suspend/resume,
- enet work proper
after the device tree and driver update to handle the clocks,
this patch could be dropped.Signed-off-by: Peng Fan
Reviewed-by: Jacky Bai
Reviewed-by: Ye Li -
Per reference mannual Rev E, correct the enet clock.
Signed-off-by: Peng Fan
Reviewed-by: Ye Li -
The clk tree should be as:
bus_aon_root------>\ /--->MU1_B
-->MU_B gate-->
bus_wakeup_root--->/ \--->MU2_Bbus_aon_root------>\ /--->MU1_A
-->MU_A gate-->
bus_wakeup_root--->/ \--->MU2_ASo need use shared count gate. And linux use MU_B,
so set MU_A clk as CLK_IGNORE_UNUSED.Signed-off-by: Peng Fan
Reviewed-by: Jacky Bai
Reviewed-by: Ye Li