23 Feb, 2016
6 commits
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Convert DPLL support code to use clk_hw pointers for reference and bypass
clocks. This allows us to use clk_hw_* APIs for accessing any required
parameters for these clocks, avoiding some locking problems at least with
DPLL enable code; this used clk_get_rate which uses mutex but isn't
good under clk_enable / clk_disable.Signed-off-by: Tero Kristo
Acked-by: Tony Lindgren
Signed-off-by: Stephen Boyd -
* clk-fixes:
clk: ti: omap3+: dpll: use non-locking version of clk_get_rate -
This patch corrects the enable register offset which is actually 0x36cc
instead of 0x36c4Signed-off-by: Srinivas Kandagatla
Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control")
Signed-off-by: Stephen Boyd -
As the code in this file is being executed within irq context in some
cases, we must avoid the clk_get_rate which uses mutex internally.
Switch the code to use clk_hw_get_rate instead which is non-locking.This fixes an issue where PM runtime will hang the system if enabled
with a serial console before a suspend-resume cycle.Signed-off-by: Tero Kristo
Tested-by: Tony Lindgren
Fixes: a53ad8ef3dcc ("clk: ti: Convert to clk_hw based provider APIs")
Signed-off-by: Stephen Boyd -
Currently the Exynos5433 (ARMv8 SoC) clock driver depends on ARCH_EXYNOS
so it is built also on ARMv7. This does not bring any kind of benefit.
There won't be a single kernel image for ARMv7 and ARMv8 SoCs (like
multi_v7 for ARMv7).Instead build clock drivers only for respective SoC's architecture.
Signed-off-by: Krzysztof Kozlowski
Acked-by: Sylwester Nawrocki
Signed-off-by: Michael Turquette
20 Feb, 2016
1 commit
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…l/git/geert/renesas-drivers into clk-next
19 Feb, 2016
2 commits
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* clk-fixes:
clk: gpio: Really allow an optional clock= DT property
Revert "clk: qcom: Specify LE device endianness" -
We mis-merged the original patch from Russell here and so the
patch went almost all the way, except that we still failed to
probe when there wasn't a clocks property in the DT node. Allow
that case by making a negative value from
of_clk_get_parent_count() into "no parents", like the original
patch did.Fixes: 7ed88aa2efa5 ("clk: fix clk-gpio.c with optional clock= DT property")
Cc: Russell King
Cc: Michael Turquette
Signed-off-by: Stephen Boyd
18 Feb, 2016
2 commits
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Add the "intc-ex" clock to the r8a7795 CPG MSSR driver.
According to information from the hardware team the INTC-EX
parent clock is CP. The next data sheet version will include
this information.Signed-off-by: Magnus Damm
Signed-off-by: Geert Uytterhoeven -
Export symbol of_clk_get_from_provider so it can be used in
loadable kernel modulesSigned-off-by: Andrew F. Davis
Signed-off-by: Michael Turquette
17 Feb, 2016
4 commits
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Enable the COMPILE_TEST to get build coverage of some of Samsung clock
controller drivers. Still some of them will be built only if
appropriate SoC is chosen (like SOC_EXYNOS4415 or ARCH_S3C64XX).Signed-off-by: Krzysztof Kozlowski
Reviewed-by: Javier Martinez Canillas
Tested-by: Javier Martinez Canillas
Reviewed-by: Andi Shyti
Signed-off-by: Michael Turquette -
We were rolling this ourselves, but clk-divider can do it now.
Signed-off-by: Eric Anholt
Signed-off-by: Michael Turquette -
Our dividers weren't being set successfully because CM_PASSWORD wasn't
included in the register write. It looks easier to just compute the
divider to write ourselves than to update clk-divider for the ability
to OR in some arbitrary bits on write.Fixes about half of the video modes on my HDMI monitor (everything
except 720x400).Cc: stable@vger.kernel.org
Signed-off-by: Eric Anholt
Signed-off-by: Michael Turquette
16 Feb, 2016
2 commits
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Cfr. commit a9ec81f4ed5c05db ("serial: sh-sci: Drop the interface
clock").Signed-off-by: Geert Uytterhoeven
Acked-by: Michael Turquette -
…mmind/linux-rockchip into clk-next
Introduction of a factor type and a variant containing a gate
to be able to also declare factor clocks in their correct
place in the clock tree instead of having to register factor
clocks in the init callback separately. And as always some more
clock-ids and non-regression fixes for mistakes introduced in
past kernel releases.
13 Feb, 2016
1 commit
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This reverts commit 329cabcecf94d8d7821e729dda284ba9dec44c87.
The commit that caused us to specify LE device endianness here,
29bb45f25ff3 (regmap-mmio: Use native endianness for read/write,
2015-10-29), has been reverted in mainline so now when we specify
LE it actively breaks big endian kernels because the byte
swapping in regmap-mmio is incorrect. Let's revert this change
because it will 1) fix the big endian kernels and 2) be redundant
to specify LE because that will become the default soon.Cc: Kevin Hilman
Tested-by: Kevin Hilman
Cc: Mark Brown
Signed-off-by: Stephen Boyd
12 Feb, 2016
6 commits
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With gdsc driver capable of handling hierarchical power domains,
specify oxili_gdsc as parent of oxilicx_gdsc.Remove all direct calls to genpd from the mmcc clock driver. The
adding and removing of subdomains is now handled from within
the gdsc driver.Signed-off-by: Rajendra Nayak
Signed-off-by: Stephen Boyd -
Add all gdsc data which are part of mmcc on msm8996 family
Signed-off-by: Rajendra Nayak
Signed-off-by: Stephen Boyd -
Add all data for the GDSCs which are part of msm8996 GCC block
Signed-off-by: Rajendra Nayak
Signed-off-by: Stephen Boyd -
Some gdscs might be controlled via voting registers and might not
really disable when the kernel intends to disable them (due to other
votes keeping them enabled)
Mark these gdscs with a flag for we do not check/wait on a disable
status for these gdscs within the kernel disable callback.Also at boot, if these GDSCs are found to be ON, we make sure we
vote for them before we inform the genpd framework about their
status. If genpd gets no users, it then disables (removes the vote)
them as part of genpd_poweroff_unused()Signed-off-by: Rajendra Nayak
Signed-off-by: Stephen Boyd -
Some gdsc power domains can have a gds_hw_controller block inside
to help ensure all slave devices within the power domain are idle
before the gdsc is actually switched off.
This is mainly useful in power domains which host a MMU, in which
case its necessary to make sure there are no outstanding MMU operations
or pending bus transactions before the power domain is turned off.In gdscs with gds_hw_controller block, its necessary to check the
gds_hw_ctrl status bits instead of the ones in gdscr, to determine
the state of the powerdomain.While at it, also move away from using jiffies and use ktime APIs
instead for busy looping on status bits.Signed-off-by: Rajendra Nayak
Signed-off-by: Stephen Boyd -
Some qcom SoCs' can have hierarchical power domains. Let the gdsc structs
specify the parents (if any) and the driver add genpd subdomains for them.Signed-off-by: Rajendra Nayak
Signed-off-by: Stephen Boyd
11 Feb, 2016
3 commits
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This patch add the support to setup the HCLK PLL output
using the "assigned-clock-rates" parameter in the device tree.If the option is not use, the clock setup by the kickstart
and/or bootloader remain unchanged.The previous kernel version did not change the clock frequency
output setup by the kickstart and/or bootloader;
this version always setup the clock frequency output to 208MHz.Signed-off-by: Sylvain Lemieux
Signed-off-by: Stephen Boyd -
* clk-fixes:
clk: versatile: mask VCO bits before writing -
The Versatile syscon ICST driver OR:s the bits into place but
forgets to mask the previous value, making the code only work
if the register is zero or giving haphazard results. Mask the
19 bits used by the Versatile syscon interface register.Regression caused and now fixed by yours truly.
Cc: Michael Turquette
Cc: Stephen Boyd
Cc: linux-clk@vger.kernel.org
Fixes: 179c8fb3c2a6 ("clk: versatile-icst: convert to use regmap")
Signed-off-by: Linus Walleij
Signed-off-by: Stephen Boyd
10 Feb, 2016
2 commits
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The following errors are display in the console during the power-on:
[ 0.000000] lpc32xx_usb_clk_init: failed to register (null) clock: -12
[ 0.000000] lpc32xx_clk_init: failed to register (null) clock: -12There is no need to register clock "0"; the first clock used is 1;
Signed-off-by: Sylvain Lemieux
Acked-by: Vladimir Zapolskiy
[sboyd@codeaurora.org: s/prepare/register/]
Signed-off-by: Stephen Boyd -
Before commit b3d192d5121f ("clk: simplify __clk_init_parent()"),
__clk_init_parent() called .get_parent() only for multi-parent
clocks. That commit changed the behavior to call .get_parent()
if available even for single-parent clocks and root clocks.It turned out a problem because there are some single-parent clocks
that implement .get_parent() callback and return non-zero index.
The SOCFPGA clock is the case; the commit broke the SOCFPGA boards.To keep the original behavior, invoke .get_parent() only when
num_parents is greater than 1.Fixes: b3d192d5121f ("clk: simplify __clk_init_parent()")
Signed-off-by: Masahiro Yamada
Reported-by: Dinh Nguyen
Signed-off-by: Stephen Boyd
09 Feb, 2016
8 commits
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We were not checking the return from devm_add_action() which can fail.
Start using the helper and devm_add_action_or_reset() and return
directly as we know that the cleanup has been done by this helper.Signed-off-by: Sudip Mukherjee
Signed-off-by: Stephen Boyd -
Add a helper function devm_add_action_or_reset() which will internally
call devm_add_action(). But if devm_add_action() fails then it will
execute the action mentioned and return the error code.Signed-off-by: Sudip Mukherjee
Acked-by: Greg Kroah-Hartman
Signed-off-by: Stephen Boyd -
As preparation for arm64 based mesongxbb, which pulls in this code once
enabling ARCH_MESON, fix a size_t vs. unsigned int type mismatch.
The loop uses a local unsigned int variable, so adopt that type,
matching the header.Fixes: 7a29a869434e ("clk: meson: Add support for Meson clock controller")
Signed-off-by: Andreas Färber
Acked-by: Carlo Caione
Signed-off-by: Stephen Boyd -
clang found a bug with the __socfpga_pll_init definition:
drivers/clk/socfpga/clk-pll-a10.c:77:15: error: '__section__' attribute only applies to functions and
global variablesThis moves the __init annotation to the right place so the function
actually gets discarded.Signed-off-by: Arnd Bergmann
Signed-off-by: Stephen Boyd -
There are two TI CDCE clock chips in this file. Move them close
together so they're easier to find.No functional change, just cosmetic.
Signed-off-by: Mike Looijmans
[sboyd@codeaurora.org: Alphabetize]
Signed-off-by: Stephen Boyd -
Simple cosmetic fix.
Signed-off-by: Mike Looijmans
Signed-off-by: Stephen Boyd -
* clk-fixes:
clk: tegra: super: Fix sparse warnings for functions not declared as static
clk: tegra: Fix sparse warnings for functions not declared as static
clk: tegra: Fix sparse warning for pll_m
clk: tegra: Use definition for pll_u override bit
clk: tegra: Fix warning caused by pll_u failing to lock
clk: tegra: Fix clock sources for Tegra210 EMC
clk: tegra: Add the APB2APE audio clock on Tegra210
clk: tegra: Add missing of_node_put()
clk: tegra: Fix PLLE SS coefficients
clk: tegra: Fix typos around clearing PLLE bits during enable
clk: tegra: Do not disable PLLE when under hardware control
clk: tegra: Fix pllx dyn step calculation
clk: tegra: pll: Fix potential sleeping-while-atomic
clk: tegra: Fix the misnaming of nvenc from msenc
clk: tegra: Fix naming of MISC registers
clk: tegra: Remove improper flags for lock_enable
clk: tegra: Fix divider on VI_I2C -
…/git/tegra/linux into clk-fixes
Pull tegra fixes from Thierry Reding:
clk: tegra: Fixes for v4.5-rc3
This set contains a bunch of miscellaneous fixes that have accumulated
over the past couple of weeks, primarily for the Tegra210 support added
in v4.5-rc1.* tag 'tegra-for-4.5-clk-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
clk: tegra: super: Fix sparse warnings for functions not declared as static
clk: tegra: Fix sparse warnings for functions not declared as static
clk: tegra: Fix sparse warning for pll_m
clk: tegra: Use definition for pll_u override bit
clk: tegra: Fix warning caused by pll_u failing to lock
clk: tegra: Fix clock sources for Tegra210 EMC
clk: tegra: Add the APB2APE audio clock on Tegra210
clk: tegra: Add missing of_node_put()
clk: tegra: Fix PLLE SS coefficients
clk: tegra: Fix typos around clearing PLLE bits during enable
clk: tegra: Do not disable PLLE when under hardware control
clk: tegra: Fix pllx dyn step calculation
clk: tegra: pll: Fix potential sleeping-while-atomic
clk: tegra: Fix the misnaming of nvenc from msenc
clk: tegra: Fix naming of MISC registers
clk: tegra: Remove improper flags for lock_enable
clk: tegra: Fix divider on VI_I2C
08 Feb, 2016
2 commits
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Signed-off-by: Yoshihiro Shimoda
Signed-off-by: Geert Uytterhoeven -
This patch adds SD[0..3] clock divider support for R-Car Gen3 SoC.
Signed-off-by: Takeshi Kihara
Signed-off-by: Dirk Behme
Tested-by: Wolfram Sang
Signed-off-by: Geert Uytterhoeven
07 Feb, 2016
1 commit
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These functions either never existed or were only used in
OF_CLK_DECLARE() macros. Remove the dead prototypes.Cc: Jyri Sarha
Signed-off-by: Stephen Boyd