02 May, 2018
1 commit
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commit 881c93c0fb73328845898344208fa0bf0d62cac6 upstream.
If the driver module is loaded when FPGA is configured, the FPGA
is reset because nconfig is pulled low (low-active gpio inited
with GPIOD_OUT_HIGH activates the signal which means setting its
value to low). Init nconfig with GPIOD_OUT_LOW to prevent this.Signed-off-by: Anatolij Gustschin
Acked-by: Alan Tull
Signed-off-by: Moritz Fischer
Cc: stable # 4.14+
Signed-off-by: Greg Kroah-Hartman
08 Feb, 2018
1 commit
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commit 0f5eb1545907edeea7672a9c1652c4231150ff22 upstream.
Both fpga_region_get_manager() and fpga_region_get_bridges() call
of_parse_phandle(), but nothing calls of_node_put() on the returned
struct device_node pointers. Make sure to do that to stop their
reference counters getting out of whack.Fixes: 0fa20cdfcc1f ("fpga: fpga-region: device tree control for FPGA")
Signed-off-by: Ian Abbott
Signed-off-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman
02 Nov, 2017
1 commit
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Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.By default all files without license information are under the default
license of the kernel, which is GPL version 2.Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if
Reviewed-by: Philippe Ombredanne
Reviewed-by: Thomas Gleixner
Signed-off-by: Greg Kroah-Hartman
19 Sep, 2017
1 commit
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It's better to be explicit and use the DRIVER_ATTR_RW() macro when
defining a driver's sysfs file.This is part of a series to drop DRIVER_ATTR() from the tree entirely.
Cc: linux-fpga@vger.kernel.org
Reviewed-by: Moritz Fischer
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman
11 Aug, 2017
4 commits
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The global spinlock `l3_remap_lock` is reinitialized every time the
"probe" function `alt_fpga_bridge_probe()` is called. It should only be
initialized once. Use `DEFINE_SPINLOCK()` to initialize it statically.Fixes: e5f8efa5c8bf ("ARM: socfpga: fpga bridge driver support")
Cc: # 4.10+
Signed-off-by: Ian Abbott
Reviewed-By: Moritz Fischer
Signed-off-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
Check return value from call to of_match_device()
in order to prevent a NULL pointer dereference.In case of NULL print error message and return -ENODEV
Signed-off-by: Gustavo A. R. Silva
Reviewed-by: Moritz Fischer
Signed-off-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
Commit a53e35db70d1 ("reset: Ensure drivers are explicit when requesting
reset lines") started to transition the reset control request API calls
to explicitly state whether the driver needs exclusive or shared reset
control behavior. Convert all drivers requesting exclusive resets to the
explicit API call so the temporary transition helpers can be removed.No functional changes.
Cc: Alan Tull
Cc: Moritz Fischer
Cc: linux-fpga@vger.kernel.org
Signed-off-by: Philipp Zabel
Acked-By: Moritz Fischer
Signed-off-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
Now that we have a custom printf format specifier, convert users of
full_name to use %pOF instead. This is preparation to remove storing
of the full path string for each node.Signed-off-by: Rob Herring
Cc: Alan Tull
Cc: Moritz Fischer
Cc: linux-fpga@vger.kernel.org
Acked-by: Moritz Fischer
Signed-off-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman
17 Jul, 2017
4 commits
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Add FPGA manager driver for loading Arria-V/Cyclone-V/Stratix-V
and Arria-10 FPGAs via CvP.Signed-off-by: Anatolij Gustschin
Reviewed-by: Andy Shevchenko
Signed-off-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
Speed up bit reversal by using hardware bit reversal
Add extra code to handle less than 4byte remnants, if anySigned-off-by: Joshua Clayton
Signed-off-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
altera-ps-spi loads FPGA firmware over SPI, using the "passive serial"
interface on Altera Arria 10, Cyclone V or Stratix V FPGAs.This is one of the simpler ways to set up an FPGA at runtime.
The signal interface is close to unidirectional SPI with lsb first.Signed-off-by: Joshua Clayton
Signed-off-by: Anatolij Gustschin
Signed-off-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
No need to get into the submenu to disable all FPGA-related config entries
Signed-off-by: Vincent Legoll
Acked-by: Moritz Fischer
Signed-off-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman
26 Apr, 2017
3 commits
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The value in the version register of the altera freeze bridge
controller changed from the beta value of 2 to the
value of 0xad000003 in the official release of the IP.
This patch supports the old and new version numbers, and the
driver's probe function will fail if neither of the supported
versions is found.Signed-off-by: Matthew Gerlach
Reviewed-by: Moritz Fischer
Signed-off-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
If fpga_region_get_manager() fails in fpga_region_program_fpga(), a
reference to the fpga_manager instance previously acquired through
fpga_region_get() is retained. Make sure to properly release it in the
error case by using a separate jump label which will call
fpga_region_put() in before returning.Signed-off-by: Tobias Klauser
Acked-by: Moritz Fischer
Signed-off-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
If either _alt_hps2fpga_enable_set() or fpga_bridge_register() fail in
alt_fpga_bridge_probe(), the clock remains enabled and prepared. Also,
in the error path for _alt_hps2fpga_enable_set() a call to
fpga_bridge_unregister() is made even though the bridge was not
registered yet.Remove the unnecessary call to fpga_bridge_unregister() and call
clk_disable_unprepare() in both error paths in order to make sure the
clock gets properly disabled and unprepared.Signed-off-by: Tobias Klauser
Acked-by: Moritz Fischer
Signed-off-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman
08 Apr, 2017
6 commits
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This adds support for the Xilinx LogiCORE PR Decoupler
soft-ip that does decoupling of PR regions in the FPGA
fabric during partial reconfiguration.Signed-off-by: Moritz Fischer
Signed-off-by: Michal Simek
Cc: Sören Brinkmann
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
This adds a platform bus driver for a fpga-mgr driver
that uses the Altera Partial Reconfiguration IP component.Signed-off-by: Matthew Gerlach
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
Adding the core functions necessary for a fpga-mgr driver
for the Altera Partial IP component. It is intended for
these functions to be used by the various bus implementations
like the platform bus or the PCIe bus.Signed-off-by: Matthew Gerlach
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
Adding timeout for maximum allowed time for FPGA to go to
operating mode after a FPGA region has been programmed.Signed-off-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
The driver loads FPGA firmware over SPI, using the "slave serial"
configuration interface on Xilinx FPGAs.Signed-off-by: Anatolij Gustschin
Acked-by: Michal Simek
Reviewed-by: Moritz Fischer
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
The ops are not changing, make them const.
Signed-off-by: Moritz Fischer
Cc: Alan Tull
Cc: linux-kernel@vger.kernel.org
Cc: linux-fpga@vger.kernel.org
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman
17 Mar, 2017
6 commits
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Replaces open-coded list_for_each() + list_entry() with macro
list_for_each_entry()Signed-off-by: Moritz Fischer
Cc: linux-fpga@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
This patch adds support to the FPGA manager for configuring the SRAM of
iCE40LM, iCE40LP, iCE40HX, iCE40 Ultra, iCE40 UltraLite and iCE40
UltraPlus devices, through slave SPI.Signed-off-by: Joel Holdsworth
Reviewed-by: Marek Vasut
Reviewed-by: Moritz Fischer
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
Add support for loading bitstreams on the Altera Cyclone II FPGA
populated on the TS-7300 board. This is done through the configuration
and data registers offered through a memory interface between the EP93xx
SoC and the FPGA via an intermediate CPLD device.The EP93xx SoC on the TS-7300 does not have direct means of configuring
the on-board FPGA other than by using the special memory mapped
interface to the CPLD. No other entity on the system can control the
FPGA bitstream.Signed-off-by: Florian Fainelli
Acked-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
Add fpga-region property to allow passing the fact that the bitstream is
encrypted to the fpga-region and ultimately to the low-level driver.Signed-off-by: Moritz Fischer
Acked-by: Michal Simek
Signed-off-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
Add support for encrypted bitstreams. For this to work the system
must be booted in secure mode.In order for on-the-fly decryption to work, the PCAP clock rate
needs to be lowered via the PCAP_RATE_EN bit.Signed-off-by: Moritz Fischer
Acked-by: Michal Simek
Signed-off-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
Fix up these sparse warnings:
drivers/fpga/fpga-mgr.c:189:21: warning: symbol '__fpga_mgr_get' was not declared. Should it be static?
drivers/fpga/fpga-bridge.c:30:12: warning: symbol 'bridge_list_lock' was not declared. Should it be static?Signed-off-by: Dinh Nguyen
Acked-by: Moritz Fischer
Signed-off-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman
10 Feb, 2017
4 commits
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This allows the driver to avoid a high order coherent DMA allocation
and memory copy. With this patch it can DMA directly from the kernel
pages that the bitfile is stored in.Since this is now a gather DMA operation the driver uses the ISR
to feed the chips DMA queue with each entry from the SGL.Signed-off-by: Jason Gunthorpe
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
Requiring contiguous kernel memory is not a good idea, this is a limited
resource and allocation can fail under normal work loads.This introduces a .write_sg op that supporting drivers can provide
to DMA directly from dis-contiguous memory and a new entry point
fpga_mgr_buf_load_sg that users can call to directly provide page
lists.The full matrix of compatibility is provided, either the linear or sg
interface can be used by the user with a driver supporting either
interface.A notable change for drivers is that the .write op can now be called
multiple times.Signed-off-by: Jason Gunthorpe
Acked-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
There is no sense in sending a bitstream we know will not work, and
with the variety of options for bitstream generation in Xilinx tools
it is not terribly clear what the correct input should be.This is particularly important for Zynq since auto-correction was
removed from the driver and the Zynq hardware only accepts a bitstream
format that is different from what the Xilinx tools typically produce.Worse, the hardware provides no indication why the bitstream fails,
it simply times out if the input is wrong.The best option here is to have the kernel print a message informing
the user they are using a malformed bistream and programming failure
isn't for any of the myriad of other reasons.Signed-off-by: Jason Gunthorpe
Acked-by: Moritz Fischer
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
The completion did not check the interrupt status to see if any error
bits were asserted, check error bits and dump some registers if things
went wrong.A few fixes are needed to make this work, the IXR_ERROR_FLAGS_MASK was
wrong, it included the done bits, which shows a bug in mask/unmask_irqs
which were using the wrong bits, simplify all of this stuff.Signed-off-by: Jason Gunthorpe
Reviewed-by: Moritz Fischer
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman
30 Nov, 2016
5 commits
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This interface was designed for streaming, but write_init's buf
argument has an unclear purpose. Define it to be the first bytes
of the bitstream. Each driver gets to set how many bytes (at most)
it wants to see. Short bitstreams will be passed through as-is, while
long ones will be truncated.The intent is to allow drivers to peek at the header before the transfer
actually starts.Signed-off-by: Jason Gunthorpe
Acked-by: Alan Tull -
It is best practice to clear and mask all interrupts before
associating the IRQ, and this should be done after the clock
is enabled.This corrects a bad result from zynq_fpga_ops_state on bootup
where left over latched values in INT_STS_OFFSET caused it to
report an unconfigured FPGA as configured.After this change the boot up operating state for an unconfigured
FPGA reports 'unknown'.Signed-off-by: Jason Gunthorpe
Acked-by: Alan Tull
Acked-by: Moritz Fischer -
socfpga uses mgr->dev for debug prints, there should be consistency
here, so standardize on that. The only other use was for dma
which can be replaced with mgr->dev.parent.Signed-off-by: Jason Gunthorpe
Acked-by: Alan Tull
Acked-by: Moritz Fischer -
Function dev_err doesn't add a newline at the end of the string. This will
lead to a hard to read kernel log.Signed-off-by: Jason Gunthorpe
Reviewed-by: Moritz Fischer
Reviewed-by: Matthias Brugger
Acked-by: Alan Tull -
Like Zynq the Altera drivers compile fine on x86 and others too,
so make it easier to compile test this stuff.A10 requires REGMAP_MMIO to compile, so be explicit rather than
relying on it via ARCH_SOCFPGA.Signed-off-by: Jason Gunthorpe
Acked-by: Alan Tull
17 Nov, 2016
1 commit
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This is a cut and paste bug. We had intended to check "sysmgr".
Fixes: e5f8efa5c8bf ("ARM: socfpga: fpga bridge driver support")
Signed-off-by: Dan Carpenter
Acked-by: Moritz Fischer
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman
11 Nov, 2016
3 commits
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Add low level driver to support reprogramming FPGAs for Altera
SoCFPGA Arria10.Signed-off-by: Alan Tull
Reviewed-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
Add a low level driver for Altera Freeze Bridges to the FPGA Bridge
framework. A freeze bridge is a bridge that exists in the FPGA
fabric to isolate one region of the FPGA from the busses while that
one region is being reprogrammed.Signed-off-by: Alan Tull
Signed-off-by: Matthew Gerlach
Signed-off-by: Greg Kroah-Hartman -
Supports Altera SOCFPGA bridges:
* fpga2sdram
* fpga2hps
* hps2fpga
* lwhps2fpgaAllows enabling/disabling the bridges through the FPGA
Bridge Framework API functions.The fpga2sdram driver only supports enabling and disabling
of the ports that been configured early on. This is due to
a hardware limitation where the read, write, and command
ports on the fpga2sdram bridge can only be reconfigured
while there are no transactions to the sdram, i.e. when
running out of OCRAM before the kernel boots.Device tree property 'init-val' configures the driver to
enable or disable the bridge during probe. If the property
does not exist, the driver will leave the bridge in its
current state.Signed-off-by: Alan Tull
Signed-off-by: Matthew Gerlach
Signed-off-by: Dinh Nguyen
Signed-off-by: Greg Kroah-Hartman