22 Jun, 2017

1 commit


12 May, 2017

3 commits

  • The register array offset for clearing an interrupt is calculated by:

    offset = (hwirq - RESERVED_IRQ_PER_MBIGEN_CHIP) / 32;

    This is wrong because the clear register array includes the reserved
    interrupts. So the clear operation ends up in the wrong register.

    This went unnoticed so far, because the hardware clears the real bit
    through a timeout mechanism when the hardware is configured in debug
    mode. That debug mode was enabled on early generations of the hardware, so
    the problem was papered over.

    On newer hardware with updated firmware the debug mode was disabled, so the
    bits did not get cleared which causes the system to malfunction.

    Remove the subtraction of RESERVED_IRQ_PER_MBIGEN_CHIP, so the correct
    register is accessed.

    [ tglx: Rewrote changelog ]

    Fixes: a6c2f87b8820 ("irqchip/mbigen: Implement the mbigen irq chip operation functions")
    Signed-off-by: MaJun
    Signed-off-by: Hanjun Guo
    Acked-by: Marc Zyngier
    Cc: Kefeng Wang
    Cc: linuxarm@huawei.com
    Cc: Wei Yongjun
    Link: http://lkml.kernel.org/r/1494561328-39514-4-git-send-email-guohanjun@huawei.com
    Signed-off-by: Thomas Gleixner

    MaJun
     
  • platform_get_resource() may return NULL, add proper
    check to avoid potential NULL dereferencing.

    Signed-off-by: Hanjun Guo
    Acked-by: Marc Zyngier
    Cc: Kefeng Wang
    Cc: linuxarm@huawei.com
    Cc: Wei Yongjun
    Cc: MaJun
    Link: http://lkml.kernel.org/r/1494561328-39514-3-git-send-email-guohanjun@huawei.com
    Signed-off-by: Thomas Gleixner

    Hanjun Guo
     
  • Some mbigens share memory regions, and devm_ioremap_resource
    does not allow to share resources which will break the probe
    of mbigen, in opposition to devm_ioremap.

    This patch restores back usage of devm_ioremap function, but
    with proper error handling and logging.

    Fixes: 216646e4d82e ("irqchip/mbigen: Fix return value check in mbigen_device_probe()")
    Signed-off-by: Hanjun Guo
    Acked-by: Marc Zyngier
    Cc: Kefeng Wang
    Cc: linuxarm@huawei.com
    Cc: Wei Yongjun
    Cc: MaJun
    Link: http://lkml.kernel.org/r/1494561328-39514-2-git-send-email-guohanjun@huawei.com
    Signed-off-by: Thomas Gleixner

    Hanjun Guo
     

30 Apr, 2017

1 commit

  • In case of error, the function devm_ioremap() returns NULL pointer
    not ERR_PTR(). Use devm_ioremap_resource() instead of devm_ioremap()
    to fix the IS_ERR() test issue.

    Fixes: 76e1f77f9c26 ("irqchip/mbigen: Introduce mbigen_of_create_domain()")
    Signed-off-by: Wei Yongjun
    Cc: Marc Zyngier
    Cc: Kefeng Wang
    Cc: Jason Cooper
    Link: http://lkml.kernel.org/r/20170427152113.31147-1-weiyj.lk@gmail.com
    Signed-off-by: Thomas Gleixner

    Wei Yongjun
     

07 Apr, 2017

3 commits

  • With the preparation of platform msi support and interrupt producer
    in commit d44fa3d46079 ("ACPI: Add support for ResourceSource/IRQ
    domain mapping"), we can add mbigen ACPI support now.

    Now that the major framework changes are ready, we just need to add
    the ACPI probe code which creates the irqdomain for devices connecting
    to it.

    In order to create the irqdomain, we need to know the number of hw
    irqs as input which is provided by mbigen. In DT case, we are using
    "num-pins" property to describe it, and we will take advantage of
    that too using _DSD in ACPI as there is no standard way of describe
    it in ACPI way, also according to the _DSD rule described in
    Documentation/acpi/DSD-properties-rules.txt, it doesn't break
    the rules.

    The DSDT is represented as below:

    For mbigen,
    Device(MBI0) {
    Name(_HID, "HISI0152")
    Name(_UID, Zero)
    Name(_CRS, ResourceTemplate() {
    Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
    })

    Name(_DSD, Package () {
    ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
    Package () {
    Package () {"num-pins", 378}
    }
    })
    }

    For devices,
    Device(SAS0) {
    Name(_HID, "HISIxxxx")
    Name(_UID, Zero)
    Name(_CRS, ResourceTemplate() {
    Memory32Fixed(ReadWrite, 0xb0030000, 0x10000)
    Interrupt(ResourceConsumer,..., "\_SB.MBI0") {12, ...}
    })
    }

    So for the devices connected to the mbigen, as we clearly say that
    it refers to a specific interrupt controller (mbigen), we can get
    the virq from mbigen's irqdomain once it's created successfully.

    Signed-off-by: Hanjun Guo
    Signed-off-by: MaJun
    Cc: Al Stone
    Cc: Darren Hart
    Cc: Lorenzo Pieralisi
    Signed-off-by: Marc Zyngier

    Hanjun Guo
     
  • Introduce mbigen_of_create_domain() to consolidate OF related
    code and prepare for ACPI later, no funtional change.

    Signed-off-by: Kefeng Wang
    Signed-off-by: Hanjun Guo
    Reviewed-by: Ma Jun
    Tested-by: Ming Lei
    Tested-by: Wei Xu
    Cc: Thomas Gleixner
    Signed-off-by: Marc Zyngier

    Kefeng Wang
     
  • Module owner will be set by driver core, so drop it.

    Signed-off-by: Kefeng Wang
    Signed-off-by: Hanjun Guo
    Reviewed-by: Ma Jun
    Tested-by: Ming Lei
    Tested-by: Wei Xu
    Cc: Marc Zyngier
    Cc: Thomas Gleixner
    Signed-off-by: Marc Zyngier

    Kefeng Wang
     

11 May, 2016

1 commit


21 Mar, 2016

1 commit

  • Each mbigen device is represented as a independent platform device. If the
    devices belong to the same mbigen hardware module, then the register space for
    these devices is the same. That leads to a resource conflict.

    The solution for this is to represent the mbigen module as a platform device
    and make the mbigen devices subdevices of that. The register space is
    associated to the mbigen module and therefor the resource conflict is avoided.

    [ tglx: Massaged changelog, cleaned up the code and removed the silly printk ]

    Signed-off-by: Ma Jun
    Cc: mark.rutland@arm.com
    Cc: jason@lakedaemon.net
    Cc: marc.zyngier@arm.com
    Cc: Catalin.Marinas@arm.com
    Cc: guohanjun@huawei.com
    Cc: Will.Deacon@arm.com
    Cc: huxinwei@huawei.com
    Cc: lizefan@huawei.com
    Cc: dingtianhong@huawei.com
    Cc: zhaojunhua@hisilicon.com
    Cc: liguozhu@hisilicon.com
    Cc: linux-arm-kernel@lists.infradead.org
    Link: http://lkml.kernel.org/r/1458203641-17172-3-git-send-email-majun258@huawei.com
    Signed-off-by: Thomas Gleixner

    MaJun
     

18 Dec, 2015

3 commits

  • Add the interrupt controller chip operation functions of mbigen chip.

    Signed-off-by: Ma Jun
    Reviewed-by: Marc Zyngier
    Signed-off-by: Marc Zyngier

    Ma Jun
     
  • For peripheral devices which connect to mbigen,mbigen is a interrupt
    controller. So, we create irq domain for each mbigen device and add
    mbigen irq domain into irq hierarchy structure.

    Signed-off-by: Ma Jun
    Reviewed-by: Marc Zyngier
    Signed-off-by: Marc Zyngier

    Ma Jun
     
  • Mbigen means Message Based Interrupt Generator(MBIGEN).

    Its a kind of interrupt controller that collects
    the interrupts from external devices and generate msi interrupt.
    Mbigen is applied to reduce the number of wire connected interrupts.

    As the peripherals increasing, the interrupts lines needed is
    increasing much, especially on the Arm64 server SOC.

    Therefore, the interrupt pin in GIC is not enough to cover so
    many peripherals.

    Mbigen is designed to fix this problem.

    Mbigen chip locates in ITS or outside of ITS.

    Mbigen chip hardware structure shows as below:

    mbigen chip
    |---------------------|-------------------|
    mgn_node0 mgn_node1 mgn_node2
    | |-------| |-------|------|
    dev1 dev1 dev2 dev1 dev3 dev4

    Each mbigen chip contains several mbigen nodes.

    External devices can connect to mbigen node through wire connecting way.

    Because a mbigen node only can support 128 interrupt maximum, depends
    on the interrupt lines number of devices, a device can connects to one
    more mbigen nodes.

    Also, several different devices can connect to a same mbigen node.

    When devices triggered interrupt,mbigen chip detects and collects
    the interrupts and generates the MBI interrupts by writing the ITS
    Translator register.

    To simplify mbigen driver,I used a new conception--mbigen device.
    Each mbigen device is initialized as a platform device.

    Mbigen device presents the parts(register, pin definition etc.) in
    mbigen chip corresponding to a peripheral device.

    So from software view, the structure likes below

    mbigen chip
    |---------------------|-----------------|
    mbigen device1 mbigen device2 mbigen device3
    | | |
    dev1 dev2 dev3

    Reviewed-by: Marc Zyngier
    Signed-off-by: Ma Jun
    Signed-off-by: Marc Zyngier

    Ma Jun