09 May, 2018

1 commit

  • commit 1bc2463cee92ef0e2034c813d5e511adeb58b5fd upstream.

    When the interrupts for a combiner span multiple registers it must be
    checked if any interrupts have been asserted on each register before
    checking for spurious interrupts.

    Checking each register seperately leads to false positive warnings.

    [ tglx: Massaged changelog ]

    Fixes: f20cc9b00c7b ("irqchip/qcom: Add IRQ combiner driver")
    Signed-off-by: Agustin Vega-Frias
    Signed-off-by: Thomas Gleixner
    Cc: Jason Cooper
    Cc: Marc Zyngier
    Cc: timur@codeaurora.org
    Cc: linux-arm-kernel@lists.infradead.org
    Cc: stable@vger.kernel.org
    Link: https://lkml.kernel.org/r/1525184090-26143-1-git-send-email-agustinv@codeaurora.org
    Signed-off-by: Greg Kroah-Hartman

    Agustin Vega-Frias
     

14 Dec, 2017

1 commit

  • [ Upstream commit e9990d70e8a063a7b894c5cbb99f630a0f41200d ]

    The comparison of u32 nregs being less than zero is never true since
    nregs is unsigned. Fix this by making nregs a signed integer.

    Fixes: f20cc9b00c7b ("irqchip/qcom: Add IRQ combiner driver")
    Signed-off-by: Colin Ian King
    Signed-off-by: Thomas Gleixner
    Cc: Marc Zyngier
    Cc: kernel-janitors@vger.kernel.org
    Cc: Jason Cooper
    Link: https://lkml.kernel.org/r/20171117183553.2739-1-colin.king@canonical.com
    Signed-off-by: Sasha Levin
    Signed-off-by: Greg Kroah-Hartman

    Colin Ian King
     

22 Jun, 2017

1 commit


19 Feb, 2017

1 commit

  • 'devm_ioremap()' returns NULL on error, not an error pointer.

    Fixes: f20cc9b00c7b ("irqchip/qcom: Add IRQ combiner driver")
    Signed-off-by: Christophe JAILLET
    Cc: marc.zyngier@arm.com
    Cc: kernel-janitors@vger.kernel.org
    Cc: jason@lakedaemon.net
    Link: http://lkml.kernel.org/r/20170218083434.2289-1-christophe.jaillet@wanadoo.fr
    Signed-off-by: Thomas Gleixner

    Christophe JAILLET
     

03 Feb, 2017

1 commit

  • Driver for interrupt combiners in the Top-level Control and Status
    Registers (TCSR) hardware block in Qualcomm Technologies chips.

    An interrupt combiner in this block combines a set of interrupts by
    OR'ing the individual interrupt signals into a summary interrupt
    signal routed to a parent interrupt controller, and provides read-
    only, 32-bit registers to query the status of individual interrupts.
    The status bit for IRQ n is bit (n % 32) within register (n / 32)
    of the given combiner. Thus, each combiner can be described as a set
    of register offsets and the number of IRQs managed.

    Signed-off-by: Agustin Vega-Frias
    Signed-off-by: Marc Zyngier

    Agustin Vega-Frias