16 Nov, 2018
1 commit
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Drop xenvm soc data, we have userspace tool stack generate correct model
compatile and this soc data will also trigger issue on i.MX8QXP.So drop it.
Signed-off-by: Peng Fan
Reviewed-by: Flynn xu
(cherry picked from commit 9be6db046ac435f2caab7ab3561ea1a66144cdda)
06 Nov, 2018
4 commits
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This patch fixes coverity issue of "unchecked return value".
Signed-off-by: Anson Huang
Reviewed-by: Bai Ping -
This patch fixes coverity issue of "improper argument type".
Signed-off-by: Anson Huang
Reviewed-by: Bai Ping -
This patch fixes coverity issue of "divide by 0".
Signed-off-by: Anson Huang
Reviewed-by: Bai Ping -
This patch fixes coverity issue of "divide by 0".
Signed-off-by: Anson Huang
Reviewed-by: Bai Ping
03 Nov, 2018
1 commit
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Update SCFW API to the following commit:
"
("430d1e3646fbe75e339e18abf2330565eac906e0")
Author: Chuck Cannon
Date: Fri Nov 2 15:25:45 2018 -0500SCF-105: RN updates.
"Signed-off-by: Ranjani Vaidyanathan
02 Nov, 2018
1 commit
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The 100MTS low bus mode can be only supported by i.MX8MQ Rev2.1 and
future TO. So necessary check is added to identify the chip revision
when doing busfreq mode switch.Signed-off-by: Bai Ping
Reviewed-by: Anson Huang
30 Oct, 2018
1 commit
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HDMI TX should keep in power on state in suspend mode.
Otherwise HDMI FW will lost.
Add flag GENPD_FLAG_ALWAYS_ON to hdmi tx power domains.Signed-off-by: Sandor Yu
29 Oct, 2018
32 commits
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Select CLKSRC_IMX_GPT for i.MX8QXP by default.
Signed-off-by: Anson Huang
Acked-by: Leonard Crestez
Reviewed-by: Bai Ping -
That caused by commit d5c4a949522f6 ("MLK-19515 soc: imx: ipc: remove
unnecessary set wake for mu") which remove irq_set_irq_wakeup directly.
Actually, we can keep that in driver without set_irq_wake() interface in
GIC driver if cherry-pick commit 4110b5cbb014e ("irqchip/gic-v3: Allow
interrupt to be configured as wake-up sources") from upstreaming kernel.Signed-off-by: Robin Gong
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For i.MX8QM/i.MX8QXP, one power domain could have several devices
inside, such as cs42888 and wm8960 both belong to pd_mclk_out0
power domain, when these two devices probed, imx8_attach_dev() will
be called and these two devices' clocks will be add to pd_mclk_out0's
clock list, then if the second device probe failed and imx8_detach_dev()
will be called, the original code will go through the whole pd_mclk_out0
power domian's clock list and delete all the clock nodes, when the
clock node are NOT belonging to this device, below kernel warning will
show out by devm_kfree() function:[ 4.998488] [] devm_kfree+0x2c/0x38
[ 5.003543] [] imx8_detach_dev+0xb4/0x14c
[ 5.009121] [] genpd_remove_device+0x70/0xe8
[ 5.014959] [] genpd_dev_pm_detach+0x3c/0xc8
[ 5.020797] [] dev_pm_domain_detach+0x20/0x28
[ 5.026722] [] i2c_device_probe+0x1d4/0x35c
[ 5.032472] [] driver_probe_device+0x220/0x2d4
[ 5.038484] [] __driver_attach+0xa4/0xa8
[ 5.043978] [] bus_for_each_dev+0x58/0x98
[ 5.049552] [] driver_attach+0x20/0x28
[ 5.054869] [] bus_add_driver+0x1c0/0x224
[ 5.060446] [] driver_register+0x68/0x108
[ 5.066024] [] i2c_register_driver+0x44/0x84
[ 5.071862] [] wm8960_i2c_driver_init+0x18/0x20
[ 5.077961] [] do_one_initcall+0x38/0x124
[ 5.083538] [] kernel_init_freeable+0x18c/0x228
[ 5.089638] [] kernel_init+0x10/0x100
[ 5.094869] [] ret_from_fork+0x10/0x18The correct operation is to just delete those clock nodes belonged
to the device being detached, to avoid this case, we can add a device
point which can be assigned to device during attach_dev phase, then
in detach_dev phase, check the device pointer to make sure ONLY delete
those clock nodes belonged to its own and keep other clock nodes in the
same power domain there.Reported-by: Chen Guoyin
Signed-off-by: Anson Huang
Reviewed-by: Bai Ping -
- Add the timeout mu msg send api.
- Use the timeout mu send message function to do the
notification when multi-vdev is enabled on one channel.Signed-off-by: Richard Zhu
-
Since MU now is NOT in WU irq domain, so there is no irq_set_wake
callback available, below message will come out during kernel boot
up:imx8mu_init: set_irq_wake failed: -6
GIC/MU now are powered off during suspend, so it is unnecessary to
call irq_set_irq_wake() for MU, we can remove it to avoid the failure
message.Signed-off-by: Anson Huang
Reviewed-by: Robin Gong -
Right now power_on always returns true even if SCFW reports a failure.
Since the target resource is still unpowered this quickly turns into a
hang when we attempt to access it.Handle this by reporting an error to the PM core instead and also print
the sc_err number to help with debugging.This fixes boot on 8qm A0: instead of hanging on boot we print an error
and refuse to probe the VPU.Signed-off-by: Leonard Crestez
Reviewed-by: Dong Aisheng -
update the noc QoS setting for CPU & VPU on i.MX8MQ.
Signed-off-by: Bai Ping
Reviewed-by: Jian Li
(cherry picked from commit 45d2dcaecce6d83e5c4a7e9488c651a05b0f05ac) -
Add PAD wakeup support for i.MX8 platforms with system
controller present, with PAD wakeup feature enabled,
the corresponding resource's power is no need to be
kept enabled when linux suspend, thus save a sub-system's
power consumption.Signed-off-by: Anson Huang
Reviewed-by: Bai Ping
(cherry picked from commit 3b5d781273b22461de9aaea337f9da9b2fdb643e) -
This patch enabled the TKT340553_SW_WORKAROUND on i.MX8QM RevB
Signed-off-by: Jason Liu
Reviewed-by: Anson Huang
(cherry picked from commit 35cfd2953a795caa93312394a05c4811c9d3bd6c) -
MU is shared between rpmsg driver and the multi-core
power management on i.MX6SX and i.MX7D, the RIE3 is
enabled by MU driver, but when rpmsg is probed, it
will call MU_Init and RIE3 will be clear and cause
multi-core power management never work, so do NOT
clear RIEn during MU initialization for i.MX6SX and
i.MX7D.Signed-off-by: Anson Huang
Reviewed-by: Peng Fan -
Add power domain support for i.MX8MM.
Signed-off-by: Bai Ping
(cherry picked from commit abcc28140e7b50db30cdc00b0b89f49530764736) -
add busfreq support on i.MX8MM. when system is running at low bus or
audio bus mode, the dram & bus clock will be reduced to a lower rate:
NOC: 150MHZ, AXI: 24MHz, AXI 20MHZ, DRAM core clock: 25MHz.when system is running at high bus mode, all the bus clock and dram
clock will be restore to the highest one.Signed-off-by: Bai Ping
Reviewed-by: Anson Huang -
To support lowest power mode for suspend, if no wakeup source
from non-secure partition is enabled, IRQSTEER can be powered
off when suspend, otherwise, IRQSTEER needs to be powered on
to support wakeup, so need to pass WU domain wakeup source
info to ATF, then ATF will decide if to power off IRQSTEER
when system suspend.Signed-off-by: Anson Huang
Reviewed-by: Bai Ping -
Let Dom0 use hvc to trap to xen to communicate with SCU.
xen could reuse the MU used by Dom0 before. By reusing
the MU in Dom0, xen has power to control resources owned
by DomU.Signed-off-by: Peng Fan
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Add MU restore function to support MU power off
in system suspend mode, need to re-initialize
MU after resume, since MU might lose power when
suspend.Signed-off-by: Anson Huang
Reviewed-by: Bai Ping -
The vendor tree does imx7 PGC management through regulator notifiers
while upstream implemented the same features using power domains. These
two drivers have entirely different interfaces with higher-level IP
blocks.Resolve this conflict by moving the old code to drivers/soc and
supporting both power-domain and regulator interfaces. This effectively
merges the two drivers and is similar to how imx6sx implements both
power domains and a regulator notifier for pcie specifically.Supporting both interfaces allows consumes to switch one-by-one, for
example by having PCI work with a power-domains reference while usb hsic
still uses the regulator enable/disable interface.Signed-off-by: Leonard Crestez
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Correct MIPI/PCIe/USB_HSIC's PGC offset based on
design RTL, the value on Reference Manual are incorrect.The correct offset should be as below:
0x800 ~ 0x83F: PGC for core0 of A7 platform;
0x840 ~ 0x87F: PGC for core1 of A7 platform;
0x880 ~ 0x8BF: PGC for SCU of A7 platform;
0xA00 ~ 0xA3F: PGC for fastmix/megamix;
0xC00 ~ 0xC3F: PGC for MIPI PHY;
0xC40 ~ 0xC7F: PGC for PCIe_PHY;
0xC80 ~ 0xCBF: PGC for USB OTG1 PHY;
0xCC0 ~ 0xCFF: PGC for USB OTG2 PHY;
0xD00 ~ 0xD3F: PGC for USB HSIC PHY;Signed-off-by: Anson Huang
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Add power domain compatible string for i.MX8MM.
Signed-off-by: Bai Ping
Reviewed-by: Anson Huang -
Enable cpu-freq driver for i.MX8MM.
Signed-off-by: Anson Huang
Reviewed-by: Bai Ping -
Add i.MX8MM SoC ID driver support.
Signed-off-by: Anson Huang
Reviewed-by: Bai Ping -
Add i.MX8MM SoC support.
Signed-off-by: Anson Huang
Reviewed-by: Bai Ping -
Use correct MU for SCFW API calls to comply with boot
container intended usage. Since ATF uses MU0 and kernel
uses MU1, update the MU id in api calls.Signed-off-by: Nitin Garg
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This fixes graphics on imx6sx by aligning closer to upstream instead of
adding new features to old bindings.Upstream adds a 4th power domain for PCI but this is is wrong: the PCI
block is in the DISPMIX domain and only PCIE_PHY is in the PCIE_PHY
power domain.Manual is not very clear on this but in section 10.4.1.4.1 there is this
statement: "The DISPLAY domain contains GIS, CSI, PXP, LCDIF, PCIe,
DCIC, and LDB. It is supplied by internal regulator."Placing pcie in a 4th power domain makes lspci hang when display is
turned off.In upstream the dispmix domain is not actually touched on 6sx so it's
always on, this is why pci seems to work.Signed-off-by: Leonard Crestez
Acked-by: Richard Zhu -
This was introduced while porting patches from imx_4.9.y. In the 4.9
branch there are specific power_on and power_off functions for PU but in
upstream this code was refactored to make the code generic for each PGC
block.Fixes: ce181a6440dc ("MLK-13479-1: ARM: imx: gpc: delay 2us instead of sw+sw2iso delay")
While we're at it remove GPU_VPU_{PUP,PND}_REQ because they're not used.
Upstream forgot to delete these bits while refactoring.Signed-off-by: Leonard Crestez
Acked-by: Richard Zhu -
With new bindings the PU regulator is fetched much later, after
imx_gpc_probe is complete. So hack the imx_pgc_power_domain_probe
function to check for fsl,ldo-bypass at this point.This issue only actually affects imx6qp because on other SOCs with a
vddpu regulator is it disabled on boot and settings are copied from
vddsoc on first enable, see commit 64dd7300a334 ("MLK-11407-3:
regulator: anatop: force vddpu to use same voltage level as vddsoc")On imx6qp however disabling the PU regulator is not allowed because of
hardware errata.Fixes: 94e8d6daea9a ("MLK-11407-1 soc: imx: gpc: enable PU bypass")
Signed-off-by: Leonard Crestez
Reviewed-by: Anson Huang -
This patch adds resources power mode dump from debugfs,
it is for i.MX SoCs which have SCFW to control overall
resources power mode, such as i.MX8QM/QXP, example
as below:croot@imx8qmmek:~# cat /sys/kernel/debug/imx_rsrc_pm/imx_rsrc_pm_summary
resource_id power_mode
----------------------------------------------
0 ON
1 ON
2 ON
3 ON
4 ON
5 ON
6 ON
7 ON
8 FAIL
9 FAIL
10 ON
11 ON
12 ON
13 ON
14 OFF.....
533 OFF
534 FAIL
535 FAIL
536 FAIL
537 FAIL
538 FAIL
539 FAIL
540 OFFSigned-off-by: Anson Huang
Reviewed-by: Bai Ping -
Because of the TO1.0 issue on i.MX8QM, we need to let DomU
know that errata, then DomU big.Little guest could work correctly.This is not that good to add compatible for xen vm machine in
imx8 soc code. Another method is to modify xen toolstack to create
the imx8qm compatible in domu dts, but this is not welcomed, from
xen maitainer's view "Domu should be not binded with a dedicated SoC".For supporting i.MX8QM, Let's first use the compatible. This might
cause qxp Domu thinking it is 8QM, but we do not support passthrough
on 8QXP, because no smmu.So it is ok to add the compatible here.
Signed-off-by: Peng Fan
Reviewed-by: Leonard Crestez -
When irq_set_irq_wake error, it means no irq wakeup capability,
showing the error msg is enough, no need to abort and cause
kernel stop.For xen, currently we do not support suspend/resume, and
no wu interrupt controller support now, so need to remove
"return err" to avoid kernel stop.Signed-off-by: Peng Fan
Reviewed-by: Anson Huang -
call scfw api get chip unique id
cat /sys/devices/soc0/soc_uid
A264080B57AC1898Signed-off-by: Frank Li
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Syncs with the following change in scfw.
Author: Chuck Cannon
Date: Mon Mar 5 07:44:27 2018 -0600SCF-22: Move SCU controls to SYSTEM. Allows AP to use SCU temp
sensor.BuildInfo:
- SCFW e56d4c0a, IMX-MKIMAGE d4e440b2, ATF 4af5ca0
- U-Boot 2017.03-imx_v2017.03_4.9.51_imx8_beta2+gf195c38Tested-by: Anson Huang
Reviewed-by: Nitin Garg
Signed-off-by: Adriana Reus -
The MU works just fine without interrupts because sc_call_rpc will poll
waiting for a response. Make this explicit because it allows easier
emulation for virtualization.The request_irq error is just reported but doesn't fail the probe,
however failing to set that irq as a wake source is fatal.This was introduced recently:
commit 3b20aa779f33 ("MLK-17072-1: soc: imx: sc: ipc: enable MU
interrupt as wakeup source")Signed-off-by: Leonard Crestez
Acked-by: Peng Fan -
Currently, on imx8mq evk board, we only support 3200mts and 667mts
frequency setpoints. So the DDR DVFS flow need to be updated accordingly.The dram pll and dram apb clock rate is changed in ATF when doing frequency,
in kernel side, we need to call the clk API to update the clock rate info
in clock tree.Signed-off-by: Bai Ping
Reviewed-by: Anson Huang
