09 Mar, 2016
3 commits
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In the Amlogic Meson8 / Meson8b platforms we have two different buses:
cbus and aobus, corresponding to 2 different power domains (regular and
always-on). On each bus a different set of registers is mapped to manage
muxes, GPIOs and in general to control a clear subset of the pins.Considering this architecture, having two different pinctrl devices, one
for each bus / power domain, makes much more sense than just having one
single device.Right now we have one single pin controller driver that uses two
different domains (represented by 'gpio' and 'gpio-ao' sub-nodes in the
DTS) to manage the set of registers on the two buses. This dual-domain
configuration is hardcoded into the driver that strictly requires one
domain for each bus in the same pin controller device.With this patch we refactor the driver to allow splitting the driver in
two parts. This change is needed to have a proper description of the HW
in the device-tree where we want to introduce aobus and cbus.Signed-off-by: Carlo Caione
Signed-off-by: Linus Walleij -
Separate functions for pins controlled by different pin controllers.
Signed-off-by: Carlo Caione
Signed-off-by: Linus Walleij -
The Kconfig currently controlling compilation of this code is:
drivers/pinctrl/Kconfig:config PINCTRL_MESON
drivers/pinctrl/Kconfig: bool...meaning that it currently is not being built as a module by anyone.
Lets remove the couple traces of modularity so that when reading the
driver there is no doubt it is builtin-only.Since module_platform_driver() uses the same init level priority as
builtin_platform_driver() the init ordering remains unchanged with
this commit.We don't replace module.h with init.h since the file already has that.
Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.
We also delete the MODULE_LICENSE tag etc. since all that information
is already contained at the top of the file in the comments.Cc: Beniamino Galvani
Cc: Carlo Caione
Cc: Masahiro Yamada
Cc: Antoine Tenart
Cc: linux-gpio@vger.kernel.org
Signed-off-by: Paul Gortmaker
Signed-off-by: Linus Walleij
05 Jan, 2016
1 commit
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This makes the driver use the data pointer added to the gpio_chip
to store a pointer to the state container instead of relying on
container_of().Cc: Beniamino Galvani
Cc: Carlo Caione
Cc: Antoine Tenart
Signed-off-by: Linus Walleij
19 Nov, 2015
1 commit
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The name .dev in a struct is normally reserved for a struct device
that is let us say a superclass to the thing described by the struct.
struct gpio_chip stands out by confusingly using a struct device *dev
to point to the parent device (such as a platform_device) that
represents the hardware. As we want to give gpio_chip:s real devices,
this is not working. We need to rename this member to parent.This was done by two coccinelle scripts, I guess it is possible to
combine them into one, but I don't know such stuff. They look like
this:@@
struct gpio_chip *var;
@@
-var->dev
+var->parentand:
@@
struct gpio_chip var;
@@
-var.dev
+var.parentand:
@@
struct bgpio_chip *var;
@@
-var->gc.dev
+var->gc.parentPlus a few instances of bgpio that I couldn't figure out how
to teach Coccinelle to rewrite.This patch hits all over the place, but I *strongly* prefer this
solution to any piecemal approaches that just exercise patch
mechanics all over the place. It mainly hits drivers/gpio and
drivers/pinctrl which is my own backyard anyway.Cc: Haavard Skinnemoen
Cc: Rafał Miłecki
Cc: Richard Purdie
Cc: Mauro Carvalho Chehab
Cc: Alek Du
Cc: Jaroslav Kysela
Cc: Takashi Iwai
Acked-by: Dmitry Torokhov
Acked-by: Greg Kroah-Hartman
Acked-by: Lee Jones
Acked-by: Jiri Kosina
Acked-by: Hans-Christian Egtvedt
Acked-by: Jacek Anaszewski
Signed-off-by: Linus Walleij
25 Jun, 2015
1 commit
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Pull pin control updates from Linus Walleij:
"Here is the bulk of pin control changes for the v4.2 series: Quite a
lot of new SoC subdrivers and two new main drivers this time, apart
from that business as usual.Details:
Core functionality:
- Enable exclusive pin ownership: it is possible to flag a pin
controller so that GPIO and other functions cannot use a single pin
simultaneously.New drivers:
- NXP LPC18xx System Control Unit pin controller
- Imagination Pistachio SoC pin controllerNew subdrivers:
- Freescale i.MX7d SoC
- Intel Sunrisepoint-H PCH
- Renesas PFC R8A7793
- Renesas PFC R8A7794
- Mediatek MT6397, MT8127
- SiRF Atlas 7
- Allwinner A33
- Qualcomm MSM8660
- Marvell Armada 395
- Rockchip RK3368Cleanups:
- A big cleanup of the Marvell MVEBU driver rectifying it to
correspond to reality
- Drop platform device probing from the SH PFC driver, we are now a
DT only shop for SuperH
- Drop obsolte multi-platform check for SH PFC
- Various janitorial: constification, grammar etcImprovements:
- The AT91 GPIO portions now supports the set_multiple() feature
- Split out SPI pins on the Xilinx Zynq
- Support DTs without specific function nodes in the i.MX driver"* tag 'pinctrl-v4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (99 commits)
pinctrl: rockchip: add support for the rk3368
pinctrl: rockchip: generalize perpin driver-strength setting
pinctrl: sh-pfc: r8a7794: add SDHI pin groups
pinctrl: sh-pfc: r8a7794: add MMCIF pin groups
pinctrl: sh-pfc: add R8A7794 PFC support
pinctrl: make pinctrl_register() return proper error code
pinctrl: mvebu: armada-39x: add support for Armada 395 variant
pinctrl: mvebu: armada-39x: add missing SATA functions
pinctrl: mvebu: armada-39x: add missing PCIe functions
pinctrl: mvebu: armada-38x: add ptp functions
pinctrl: mvebu: armada-38x: add ua1 functions
pinctrl: mvebu: armada-38x: add nand functions
pinctrl: mvebu: armada-38x: add sata functions
pinctrl: mvebu: armada-xp: add dram functions
pinctrl: mvebu: armada-xp: add nand rb function
pinctrl: mvebu: armada-xp: add spi1 function
pinctrl: mvebu: armada-39x: normalize ref clock naming
pinctrl: mvebu: armada-xp: rename spi to spi0
pinctrl: mvebu: armada-370: align spi1 clock pin naming
pinctrl: mvebu: armada-370: align VDD cpu-pd pin naming with datasheet
...
10 Jun, 2015
1 commit
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Currently, pinctrl_register() just returns NULL on error, so the
callers can not know the exact reason of the failure.Some of the pinctrl drivers return -EINVAL, some -ENODEV, and some
-ENOMEM on error of pinctrl_register(), although the error code
might be different from the real cause of the error.This commit reworks pinctrl_register() to return the appropriate
error code and modifies all of the pinctrl drivers to use IS_ERR()
for the error checking and PTR_ERR() for getting the error code.Signed-off-by: Masahiro Yamada
Acked-by: Patrice Chotard
Acked-by: Thierry Reding
Acked-by: Heiko Stuebner
Tested-by: Mika Westerberg
Acked-by: Mika Westerberg
Acked-by: Lee Jones
Acked-by: Sören Brinkmann
Acked-by: Laurent Pinchart
Acked-by: Ray Jui
Acked-by: Antoine Tenart
Acked-by: Hongzhou Yang
Acked-by: Wei Chen
Signed-off-by: Linus Walleij
19 May, 2015
1 commit
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The num_pins field in the struct meson_domain_data must include also the
missing pins in the Meson8b SoC, otherwise the GPIO pin mapping is
broken on this platform. Avoid also the dinamic allocation for GPIOs.Signed-off-by: Carlo Caione
Signed-off-by: Linus Walleij
07 Apr, 2015
3 commits
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This patch adds support for the AmLogic Meson8b SoC.
Signed-off-by: Carlo Caione
Acked-by: Beniamino Galvani
Signed-off-by: Linus Walleij -
Add the compatible string for Meson8b in Meson pinctrl documentation
and add new information for Meson8b in source code comments.Signed-off-by: Carlo Caione
Acked-by: Beniamino Galvani
Signed-off-by: Linus Walleij -
This patch introduces a new PIN macro and few small modifications to
simplify and shorten the Meson pinctrl drivers and cleanup the support
file for the AmLogic Meson8 SoC.Signed-off-by: Carlo Caione
Acked-by: Beniamino Galvani
Signed-off-by: Linus Walleij
26 Jan, 2015
1 commit
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This is a driver for the pinmux and GPIO controller available in
Amlogic Meson SoCs. It currently supports only Meson8, however the
common code should be generic enough to work also for other SoCs after
having defined the proper set of functions and groups.GPIO interrupts are not supported at the moment due to lack of
documentation.Signed-off-by: Beniamino Galvani
Signed-off-by: Linus Walleij
