Eric Lee / smarc-fsl-linux-kernel

16 Feb, 2016

1 commit

  • 41bd0c52c   pinctrl: zynq: fix typo in group name for qspi1 ... Browse Code »

    Due to a typo Zynq pin controller does not set pin function of qspi1
    when using function qspi1. So pin group for qspi1 has to be renamed to
    "qspi1_0_grp" as outlined in the corresponding bindings documentation.

    This also removes kernel message:
    zynq-pinctrl 700.pinctrl: invalid group "qspi1_0_grp" for function "qspi1"

    Signed-off-by: Helmut Buchsbaum
    Acked-by: Sören Brinkmann
    Signed-off-by: Linus Walleij

    Helmut Buchsbaum
     

01 Nov, 2015

1 commit

30 Oct, 2015

1 commit

  • 13e3008fa   pinctrl: zynq: Initialize early ... Browse Code »

    Supplying pinmux configuration for e.g. gpio pins leads to deferred
    probes because the pinctrl device is probed much later than gpio.
    Move the init call to a much earlier stage so it probes before the
    devices that may need it.

    Signed-off-by: Mike Looijmans
    Tested-by: Sören Brinkmann
    Signed-off-by: Linus Walleij

    Mike Looijmans
     

25 Aug, 2015

1 commit

  • 2fe2918fa   pinctrl: zynq: Fix typos in smc0_nand_grp and smc0_nor_grp ... Browse Code »

    Group names should be smc0_nand_grp and smc0_nor_grp, otherwise you'll
    get errors like this if you try to pinmux them via the devicetree:
    zynq-pinctrl 700.pinctrl: invalid group "smc0_nand_grp" for function "smc0_nand"

    Probably a typo while creating these tables.

    Signed-off-by: Mike Looijmans
    Acked-by: Sören Brinkmann
    Acked-by: Moritz Fischer
    Signed-off-by: Linus Walleij

    Mike Looijmans
     

10 Jun, 2015

1 commit

  • 323de9efd   pinctrl: make pinctrl_register() return proper error code ... Browse Code »

    Currently, pinctrl_register() just returns NULL on error, so the
    callers can not know the exact reason of the failure.

    Some of the pinctrl drivers return -EINVAL, some -ENODEV, and some
    -ENOMEM on error of pinctrl_register(), although the error code
    might be different from the real cause of the error.

    This commit reworks pinctrl_register() to return the appropriate
    error code and modifies all of the pinctrl drivers to use IS_ERR()
    for the error checking and PTR_ERR() for getting the error code.

    Signed-off-by: Masahiro Yamada
    Acked-by: Patrice Chotard
    Acked-by: Thierry Reding
    Acked-by: Heiko Stuebner
    Tested-by: Mika Westerberg
    Acked-by: Mika Westerberg
    Acked-by: Lee Jones
    Acked-by: Sören Brinkmann
    Acked-by: Laurent Pinchart
    Acked-by: Ray Jui
    Acked-by: Antoine Tenart
    Acked-by: Hongzhou Yang
    Acked-by: Wei Chen
    Signed-off-by: Linus Walleij

    Masahiro Yamada
     

02 Jun, 2015

2 commits

01 Jun, 2015

2 commits

19 May, 2015

1 commit

06 May, 2015

1 commit

  • 83a21727c   pinctrl: zynq: configure SPI SSx pins separately ... Browse Code »

    Since SCLK, MISO and MOSI are the only mandatory signals at Zynq's SPI
    interfaces, SS0, SS1 and SS2 have to be configured separately as they may
    be used as simple GPIO lines.

    This, of course, has to be considered in the devicetree, so pin controller
    configuration for e.g. an SPI0 using SS0 and SS1 only might look like the
    following snippet (derived from the example of chapter "17.5.3
    MIO/EMIO" Routing of Zynq-7000 TRM UG585). So MIO20 can now be used
    as GPIO instead of being occupied by SPI0 SS2 function. Note the separate
    pinmux function for the slave select signals:

    pinctrl_spi0_default: spi0-default {
    mux_spi {
    function = "spi0";
    groups = "spi0_0_grp";
    };

    mux_ss {
    function = "spi0_ss";
    groups = "spi0_0_ss0_grp", "spi0_0_ss1_grp";
    }

    conf-output {
    pins = "MIO16", "MIO21";
    slew-rate = ;
    bias-disable;
    low-power-disable;
    io-standard = ;
    };

    conf-input {
    pins = "MIO17";
    slew-rate = ;
    bias-high-impedance;
    low-power-disable;
    io-standard = ;
    };

    conf-select {
    pins = "MIO18", "MIO19";
    slew-rate = ;
    bias-pull-up;
    low-power-disable;
    io-standard = ;
    };
    };

    pinctrl_gpio0_default {
    mux {
    function = "gpio0";
    groups = "gpio0_20_grp"
    };

    conf {
    pins = "MIO20";
    slew-rate = ;
    bias-pull-up;
    low-power-disable;
    io-standard = ;
    };
    };

    Signed-off-by: Helmut Buchsbaum
    Acked-by: Sören Brinkmann
    Signed-off-by: Linus Walleij

    Helmut Buchsbaum
     

30 Jan, 2015

2 commits

  • 4f06266a6   pinctrl: hide PCONFDUMP in #ifdef ... Browse Code »

    The zynq and qcom-spmi pinctrl drivers both use pin_config_item arrays
    to provide extra interfaces in debugfs. This structure and the
    PCONFDUMP macro are not defined if CONFIG_DEBUG_FS is turned off,
    so we get build errors like:

    pinctrl/qcom/pinctrl-spmi-gpio.c:139:37: error: array type has incomplete element type
    static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = {
    ^
    pinctrl/qcom/pinctrl-spmi-gpio.c:140:2: error: implicit declaration of function 'PCONFDUMP' [-Werror=implicit-function-declaration]
    PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true),
    ^
    pinctrl/qcom/pinctrl-spmi-gpio.c:139:37: warning: 'pmic_conf_items' defined but not used [-Wunused-variable]
    static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = {

    Lacking any better idea to solve this nicely, this patch uses #ifdef
    to hide the structures, just like the pinctrl core does.

    Signed-off-by: Arnd Bergmann
    Signed-off-by: Linus Walleij

    Arnd Bergmann
     
  • 8090f7917   pinctrl: zynq: Fix usb0 pins ... Browse Code »

    Fix usb0 pin 19 -> 29 (matching ethernet1 pins and manual).
    Pin 19 is used for ethernet0 on the Parallella board.

    Fixes: add958cee967 ("pinctrl: Add driver for Zynq")
    Signed-off-by: Andreas Färber
    Reviewed-by: Soren Brinkmann
    Signed-off-by: Linus Walleij

    Andreas Färber
     

14 Jan, 2015

1 commit

  • f684e4ac9   pinctrl: pinconf-generic: loose DT dependence ... Browse Code »

    New pin controllers such as ACPI-based may also have custom properties
    to parse, and should be able to use generic pin config. Let's make the
    code compile on !OF systems and rename members a bit to underscore it
    is custom parameters and not necessarily DT parameters.

    This fixes a build regression for x86_64 on the zeroday kernel builds.

    Reported-by: kbuild test robot
    Reviewed-and-tested-by: Soren Brinkmann
    Signed-off-by: Linus Walleij

    Linus Walleij
     

12 Jan, 2015

1 commit

  • add958cee   pinctrl: Add driver for Zynq ... Browse Code »

    This adds a pin-control driver for Zynq.

    Changes since v2:
    - driver-specific DT properties are passed to the core in two arrays,
    one for the actual DT parsing one for the debugfs representation.
    Issue a compiler warning when the number of entries is not the same
    for both arrays.

    Changes since v1:
    - fix EMIO_SD1_CD pin name
    - add USB to pinmux options

    changes since RFCv2:
    - let Zynq select PINCTRL_ZYNQ. Boot hangs when pinctrl information is
    present in DT but no driver available.
    - add #defines to get rid of magical constants
    - add commas at end of initializers
    - separate changes in mach-zynq in separate patch
    - add driver specific io-standard DT property
    - refactored pinconf set function to not require arguments for
    argument-less properties
    - squash other patches in
    - support for IO-standard property
    - support for low-power mode property
    - migration to pinconf_generic_dt_node_to_map_all()
    - use newly created infrastructure to add pass driver-specific DT
    params to pinconf-generic

    changes since RFC:
    - use syscon/regmap to access registers in SLCR space
    - rebase to 3.18: rename enable -> set_mux
    - add kernel-doc
    - support pinconf
    - supported attributes
    - pin-bias: pull up, tristate, disable
    - slew-rate: 0 == slow, 1 == fast; generic pinconf does not display
    argument

    Signed-off-by: Soren Brinkmann
    Tested-by: Andreas Färber
    Signed-off-by: Linus Walleij

    Soren Brinkmann