25 Aug, 2015
2 commits
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We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.Cc: Daniel Thompson
Signed-off-by: Stephen Boyd -
Mostly converted with the following snippet:
@@
struct clk_hw *E;
@@-__clk_get_flags(E->clk)
+clk_hw_get_flags(E)Acked-by: Tero Kristo
Cc: Maxime Ripard
Cc: Max Filippov
Acked-by: Sebastian Hesselbarth
Cc: Daniel Thompson
Cc: Coquelin
Signed-off-by: Stephen Boyd
03 Jul, 2015
1 commit
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If stm32f4_rcc_lookup() is called with primary == 0 and secondary == 192
then it will read beyond the end of the table array due to an out-by-one
error in the range check.In addition to the fixing the inequality we also modify the r.h.s. to
make it even more explicit that we are comparing against the size of
table in bits.Reported-by: Dan Carpenter
Signed-off-by: Daniel Thompson
Acked-by: Maxime Coquelin
Fixes: 358bdf892f6b ("clk: stm32: Add clock driver for STM32F4[23]xxx devices")
Signed-off-by: Stephen Boyd
23 Jun, 2015
1 commit
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The driver supports decoding and statically modelling PLL state (i.e.
we inherit state from bootloader) and provides support for all
peripherals that support simple one-bit gated clocks. The covers all
peripherals whose clocks come from the AHB, APB1 or APB2 buses.It has been tested on an STM32F429I-Discovery board. The clock counts
for TIM2, USART1 and SYSTICK are all set correctly and the wall clock
looks OK when checked with a stopwatch. I have also tested a prototype
driver for the RNG hardware. The RNG clock is correctly enabled by the
framework (also did inverse test and proved that by changing DT to
configure the wrong clock bit then we observe the RNG driver to fail).Signed-off-by: Daniel Thompson
Reviewed-by: Maxime Coquelin
[sboyd@codeaurora.org: Silence sparse warnings]
Signed-off-by: Stephen Boyd