23 Feb, 2016
1 commit
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There are some Arria10 clocks of type "altr,socfpga-a10-perip-clk" that can
have multiple parents. Fix up the __socfpga_periph_init() to call
of_clk_parent_fill() that will return the appropriate number of parents.Also, update __socfpga_gate_init() to call of_clk_parent_fill() helper
function.Signed-off-by: Dinh Nguyen
Signed-off-by: Stephen Boyd
09 Feb, 2016
1 commit
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clang found a bug with the __socfpga_pll_init definition:
drivers/clk/socfpga/clk-pll-a10.c:77:15: error: '__section__' attribute only applies to functions and
global variablesThis moves the __init annotation to the right place so the function
actually gets discarded.Signed-off-by: Arnd Bergmann
Signed-off-by: Stephen Boyd
25 Aug, 2015
1 commit
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The debug base clock can be bypassed from the main PLL to the OSC1 clock.
The bypass register is the staysoc1(0x10) register that is in the clock
manager.This patch adds the option to get the correct parent for the debug base
clock.Signed-off-by: Dinh Nguyen
Signed-off-by: Stephen Boyd
29 Jul, 2015
1 commit
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Convert the code to use GENMASK() helper instead of div_mask() macro.
Signed-off-by: Andy Shevchenko
Acked-by: Dinh Nguyen
Signed-off-by: Stephen Boyd
21 Jul, 2015
1 commit
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Clock provider drivers generally shouldn't include clk.h because
it's the consumer API. Remove the include here because this is a
provider driver. The clkdev.h include isn't used either, remove
it and add in slab.h to make sure things keep compiling.Acked-by: Dinh Nguyen
Signed-off-by: Stephen Boyd
10 Jun, 2015
1 commit
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This line was indented too far.
Signed-off-by: Dan Carpenter
Acked-by: Dinh Nguyen
Signed-off-by: Michael Turquette
06 Jun, 2015
1 commit
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Use of_clk_parent_fill to fill in the parent clock's array.
Signed-off-by: Dinh Nguyen
Signed-off-by: Stephen Boyd
22 May, 2015
2 commits
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The clocks on the Arria 10 platform is a bit different than the
Cyclone/Arria 5 platform that it should just have it's own
driver.Signed-off-by: Dinh Nguyen
Signed-off-by: Stephen Boyd -
There are 5 possible parent clocks for the SoCFPGA Arria10. Move the define
SYSMGR_SDMMC_CTRL_SET and streq() to clk.h so that the Arria clock driver
can use.Signed-off-by: Dinh Nguyen
Signed-off-by: Stephen Boyd
15 May, 2015
2 commits
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drivers/clk/socfpga/clk-periph.c:79:39: warning: Using plain integer as NULL pointer
Cc: Dinh Nguyen
Signed-off-by: Stephen Boyd -
drivers/clk/socfpga/clk-gate.c:227:40: warning: Using plain integer as NULL pointer
Cc: Dinh Nguyen
Signed-off-by: Stephen Boyd
13 May, 2014
2 commits
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…fpga-next into clk-next-socfpga
Adds support getting the divider registers for the MAIN PLL that was once
thought to be hidden. -
The C0(mpu_clk), C1(main_clk), and C2(dbg_base_clk) outputs from the main
PLL go through a pre-divider before coming into the system. These registers
were hidden for the CycloneV platform, but are now used for the ArriaV
platform.This patch updates the clock driver to read the div-reg property for the
socfpga-periph-clk clocks. Also moves the div_mask define to clk.h for re-use.Signed-off-by: Dinh Nguyen
01 May, 2014
1 commit
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commit [1771b10d6 clk: respect the clock dependencies in of_clk_init]
exposed a flaw in the socfpga clock driver and prevents the platform
from booting on 3.15-rc1.Because the "altr,clk-mgr" is not really a clock, it should not be using
CLK_OF_DECLARE, instead we should be mapping the clk-mgr's base address
one of the functional clock init function. Use the socfpga_pll_init function
to map the clk_mgr_base_addr as this clock should always be initialized first.Signed-off-by: Dinh Nguyen
Tested-by: Pavel Machek
19 Mar, 2014
1 commit
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WARNING: drivers/clk/socfpga/built-in.o(.data+0xc0): Section mismatch in
reference from the variable socfpga_child_clocks to the function
.init.text:socfpga_pll_init()
The variable socfpga_child_clocks references
the function __init socfpga_pll_init()
If the reference is valid then annotate the
variable with __init* or __refdata (see linux/init.h) or name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_consoleWARNING: drivers/clk/socfpga/built-in.o(.data+0x184): Section mismatch in
reference from the variable socfpga_child_clocks to the function
.init.text:socfpga_periph_init()
The variable socfpga_child_clocks references
the function __init socfpga_periph_init()
If the reference is valid then annotate the
variable with __init* or __refdata (see linux/init.h) or name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_consoleWARNING: drivers/clk/socfpga/built-in.o(.data+0x248): Section mismatch in
reference from the variable socfpga_child_clocks to the function
.init.text:socfpga_gate_init()
The variable socfpga_child_clocks references
the function __init socfpga_gate_init()
If the reference is valid then annotate the
variable with __init* or __refdata (see linux/init.h) or name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_consoleReported-by: Mike Turquette
Signed-off-by: Dinh Nguyen
Signed-off-by: Mike Turquette
27 Feb, 2014
2 commits
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The PLLs can be from 3 different sources: osc1, osc2, or the f2s_ref_clk.
Update the clock driver to be able to get the correct parent.Signed-off-by: Dinh Nguyen
Cc: Steffen Trumtrar
Signed-off-by: Mike Turquette -
Use 64-bit integer for calculating clock rate. Also use do_div for the
64-bit division.Signed-off-by: Graham Moore
Signed-off-by: Dinh Nguyen
Cc: Steffen Trumtrar
Signed-off-by: Mike Turquette
19 Feb, 2014
7 commits
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The clk-phase property is used to represent the 2 clock phase values that is
needed for the SD/MMC driver. Add a prepare function to the clk_ops, that will
use the syscon driver to set sdmmc_clk's phase shift that is located in the
system manager.Signed-off-by: Dinh Nguyen
Acked-by: Zhangfei Gao
Acked-by: Jaehoon Chung
---
v9: none
v8: Use degrees in the clk-phase binding property
v7: Add dts property to represent the clk phase of the sdmmc_clk. Add a
prepare function to the gate clk that will toggle clock phase setting.
Remove the "altr,socfpga-sdmmc-sdr-clk" clock type.
v6: Add a new clock type "altr,socfpga-sdmmc-sdr-clk" that will be used to
set the phase shift settings.
v5: Use the "snps,dw-mshc" binding
v4: Use the sdmmc_clk prepare function to set the phase shift settings
v3: Not use the syscon driver because as of 3.13-rc1, the syscon driver is
loaded after the clock driver.
v2: Use the syscon driver -
Move the different kinds of clocks into their own files. The reason is to aid
readability of the code. This also goes along with the other SoC-specific
clock drivers.The split introduces new structs for the three types of clocks and uses them.
Other changes are not done to the code.Signed-off-by: Steffen Trumtrar
Signed-off-by: Dinh Nguyen -
It should be SOCFPGA instead of SOCFGPA.
Signed-off-by: Steffen Trumtrar
Signed-off-by: Dinh Nguyen -
The clk_name field from the socfpga_clk struct is unused.
Remove it.Signed-off-by: Steffen Trumtrar
Signed-off-by: Dinh Nguyen -
The only thing that socfpga_init_clocks was doing is setting up the smp_twd clk.
Now that twd-timer's clock phandle is populated in the DTS, we can remove
this function.Signed-off-by: Dinh Nguyen
Acked-by: Arnd Bergmann -
After the patch:
"clk: socfpga: Map the clk manager base address in the clock driver"The clk->name field in socfpga_clk_recalc_rate() was getting cleared. Replace
looking for the GPIO_DB_CLK by its divider offset instead.Also rename the define SOCFPGA_DB_CLK_OFFSET -> SOCFPGA_GPIO_DB_CLK_OFFSET, as
this represents the GPIO_DB_CLK.Signed-off-by: Dinh Nguyen
-
The clk manager's base address was being mapped in SOCFPGA's arch code and
being extern'ed out to the clock driver. This method is not correct, and the
arch code was not really doing anything with that clk manager anyways.This patch moves the mapping of the clk manager's base address in the clock
driver itself. Cleans up CLK_OF_DECLARE() into a single registration of all
the clocks.Suggested-by: Arnd Bergmann
Signed-off-by: Dinh Nguyen
Acked-by: Arnd Bergmann
---
v2: Use a static declaration for the clk_mgr_base_addr. Clean up the
CLK_OF_DECLARE() as suggested by Arnd.
20 Dec, 2013
1 commit
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'div_reg' is a pointer. Assign NULL instead of 0.
Signed-off-by: Sachin Kamat
Acked-by: Dinh Nguyen
Signed-off-by: Mike Turquette
28 Nov, 2013
1 commit
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The function socfpga_clk_init() can support clocks that do not have a divider
register, but a fixed-divider that can be read from DTS. Therefore, the "reg"
property is not a failing condition for socfpga_clk_init().Signed-off-by: Dinh Nguyen
Signed-off-by: Mike Turquette
08 Oct, 2013
1 commit
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The SD/MMC clock is named "sdmmc_clk", and NOT "mmc_clk". Because of this,
the SD driver was getting the incorrect clock value. This prevented the
SD driver from initializing correctly.Signed-off-by: Dinh Nguyen
CC: Arnd Bergmann
CC: Olof Johansson
Reviewed-by: Pavel Machek
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Mike Turquette
12 Jun, 2013
1 commit
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Add support to gate the clocks that directly feed peripherals. For clocks
with multiple parents, add the ability to determine the correct parent,
and also set parents. Also add support to calculate and set the clocks'
rate.Signed-off-by: Dinh Nguyen
Reviewed-by: Pavel Machek
Acked-by: Mike Turquette
Cc: Mike Turquette
CC: Arnd Bergmann
CC: Olof Johansson
Cc: Pavel Machek
CC:v4:
- Add Acked-by: Mike Turquettev3:
- Addressed comments from Pavelv2:
- Fix space/indent errors
- Add streq for strcmp == 0
Signed-off-by: Olof Johansson
15 Apr, 2013
1 commit
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With this patch, the socfpga clk driver is able to query the clock and clock
rates appropriately.Signed-off-by: Dinh Nguyen
Reviewed-by: Pavel Machek
Signed-off-by: Olof Johansson
19 Jul, 2012
1 commit
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Adding core definitions for Altera's SOCFPGA ARM platform.
Mininum support for Altera's SOCFPGA Cyclone 5 hardware.Signed-off-by: Dinh Nguyen
Reviewed-by: Pavel Machek
Reviewed-by: Rob Herring
Reviewed-by: Thomas Petazzoni
Signed-off-by: Arnd Bergmann