23 Feb, 2017
40 commits
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export this for 'make headers_install'
Signed-off-by: Robby Cai
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export this for 'make headers_install'
Signed-off-by: Robby Cai
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Add mxc_asrc.h to Kbuild. otherwise this header is not installed by
"make headers_install INSTALL_HDR_PATH=XXX".Signed-off-by: Shengjiu Wang
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Add v4l2 and dcic head file.
Signed-off-by: Sandor Yu
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add wm8962 headphone detect gpio for imx6sx-sdb board
Signed-off-by: Zidan Wang
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add ssiwm8962 sound card support for imx6qdl-sabresd board
Signed-off-by: Zidan Wang
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add spdif sound card support for imx6sl-evk board
Signed-off-by: Zidan Wang
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add ssiwm8962 sound card support for imx6sl-evk board
Signed-off-by: Zidan Wang
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Fix a typo for clock name 'pll1_bypass_src'.
Signed-off-by: Bai Ping
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Enable the device cooling device in the defconfig.
Signed-off-by: Bai Ping
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Enable devfreq cooling to trigger GPU freq change when
hot trip is reached.Make sure thermal driver loaded after cpufreq is loaded,
otherwise, cpu_cooling will not get valid cpufreq table,
hence cpu_cooling will be not working.Signed-off-by: Bai Ping
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add .get_trend callback to determine the thermal raise/fall trend,
when the temp great than a threshold, drop to the lowest trend
(THERMAL_TREND_DROP_FULL).Signed-off-by: Bai Ping
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This pacth re-write part of the code the support i.MX6 and i.MX7
in thermal driver. the TEMPMON module in i.MX6 and i.MX7 can provide
the same funtion, but has different register offset and bitfield define.Signed-off-by: Bai Ping
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LDO2p5 cannot be disabled in low power idle mode when the USB driver
enables VBUS wakeup. To identify when LDO2p5 can be disabled add a dummy
regulator that the USB driver will enable when VBUS wakeup is required.This patch is copied from commit 7d849e4d9ebca3c as code the structure has
changed too many. directly cherry-pick has too many conflicts to resolveSigned-off-by: Bai Ping
(cherry picked from commit 25a42aeb8eeb0b894a70e1a0f6750ced39830a46) -
Add low power idle support for i.MX6SL.
Signed-off-by: Bai Ping
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On i.MX6SL, we must make sure ARM:IPG clock ratio is within 12:5 when entering
wait mode. If the system is in low_bus_freq_mode, the IPG is at 12MHz
according the busfreq code. So the max rate of ARM is 28.8MHz when entering
wait mode. As there is no way run at this clk rate, so set ARM to run from
24MHz OSC.Signed-off-by: Bai Ping
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Add busfreq support for i.MX6SL SOC. we support three
busfreq mode (high_bus_freq_mode/low_bus_freq_mode and
audio_bus_freq_mode).Signed-off-by: Bai Ping
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Add busfreq device node for imx6sl.
Signed-off-by: Bai Ping
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On different platforms, the CPU power down/up timing may be
different because of different requirements or different
implementations in hardware, so we need to support dynamic
setting of these timing, board level dtb file will provide
these settings, and GPC driver need to read them and set them
to the hardware.Signed-off-by: Anson Huang
(cherry picked from commit b0145b4e8556621cbe0d72e56cec5b04454db6c2) -
The 'PLL1_SYS' and 'PLL1_SW' clks are used by the cpufreq
driver to do dynamic frequency changing procedure.The 'CLK_SET_PARENT_GATE' should not be set for 'PLL1_SW'
clk, this clock's prepare_count is not zero all the time.change the clk type of 'PLL1_SYS' to fixed_factor. due to
the hardware limit, when changing the ARM_PODF. This clock's
output should not be gated.Signed-off-by: Bai Ping
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The pll1_bypass and pll1_bypass_src clock index in cpu node
should be IMX6SX_PLL1_BYPASS and IMX6SX_PLL1_BYPASS_SRC,
so correct this.Signed-off-by: Bai Ping
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For low power idle with ARM power gated, per hardware requirement,
there must be no interrupt coming during the power down
process of ARM core, so RBC counter is enabled to hold interrupts.However, the previous setting of RBC counter is 1, which is ~30us,
but the hardware design recommend a ~90us is required during ARM
core power down, so we update the RBC counter value to 4(~120us) here.Previous delay loop to make sure RBC is actually enabled, 3us is
needed, but the loop value assume ARM is running @1GHz, but actually
ARM is running @24MHz now, so we need to update the loop value
according to ARM speed.The ARM power up timing is based on IPG / 2048, IPG is 1.5MHz during
low power idle, so the total latency of cpuidle exit should be
updated accordingly.Signed-off-by: Anson Huang
(cherry picked from commit 4e1fd49da5e87c5cc23f053692e8d7648a4d4b21) -
If in low power idle, we use the RC-OSC to reduce the power consumption,
the RC-OSC freq need to be adjusted, otherwise, the RC-OSC freq is not
very accurate. It may lead to system instability issue.Signed-off-by: Bai Ping
(cherry picked from commit 8a93ab44e98bcc6611170734b829cd8d140dd722) -
This bit is used to keep the ARM Platform memory clocks enabled if
an interrupt is pending when entering low power mode. This bit should
always bet set when the CCM_CLPCR_LPM bits are set to 01(WAIT Mode) or
10 (STOP mode) without power gating.Signed-off-by: Bai Ping
(cherry picked from commit 0272868641041c5a9eb1b3476660711bb5cd69e4) -
Add the low power idle support on i.MX6UL. The ANATOP can enter low
power when all PLLs are powered down. If need entering low power idle
with LDO_2P5 and LDO_1P1 power down and other anatop module in low
power mode, add "uart_from_osc' on command line to make sure the UART
clk is from osc to let the PLL3 power down when entering low power idle.Signed-off-by: Bai Ping
(cherry picked from commit 5215cba66938fd09f44e61b2c7b7ae0ef0629c2f) -
Enable the busfreq support on i.MX6UL EVK board. The
busfreq support below 3 busfreq mode:* high_bus_mode: MMDC 400MHz
* audio_bus_mode: MMDC 50MHz
* low_bus_mode: MMDC 24MHzSigned-off-by: Bai Ping
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According to the latest reference manual, the default AXI clock rate
should be 264MHz. Soucre AXI/AHB from pll2_bus to get the required
clock rate.Signed-off-by: Bai Ping
(cherry picked from commit d7560da7baee7a14ecb33d51182bbdc485ee6d7d) -
Cherry-pick below patch:
ENGR00317981 ARM: dts: imx: apply ENET IRQ workaround for sabresd board
This a forward porting of commit (ENGR00313685-15 ARM: dts: imx: apply
ENET IRQ workaround for sabresd board) from imx_3.10.y to imx_3.14.y.Signed-off-by: Shawn Guo
Signed-off-by: Anson Huang -
Cherry-pick below patch:
ENGR00317981: ARM: dts: add dumb dts for enetirq and ldo
Add a couple of dumb dts files for enetirq and ldo cases, which are
asked by Yocto build for 3.14 kernel.Signed-off-by: Shawn Guo
Signed-off-by: Anson Huang -
send a message to our remote processor, and tell remote
processor about this channelSigned-off-by: Richard Zhu
(cherry picked from commit 2708c004a60c5b6da020803ee9291b83984d4a65) -
AXI clk should be always enabled, as many peripheral
devices need this clk to be on, especially for busfreq,
AXI podf change needs AXI clk and its parent on.Signed-off-by: Anson Huang
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Update IPU and display property, make sure these dts files can
pass build.Signed-off-by: Sandor Yu
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Add IPU, HDMI and LDB support.
Signed-off-by: Sandor Yu
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Enable IPU, HDMI and LDB.
Signed-off-by: Sandor Yu
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Forward imx_3.14.y IPU and display drivers to 4.1 kernel.
This includes IPU core driver, display driver, LDB and HDMI driver.Signed-off-by: Sandor Yu
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When VPU is running at 352MHz, SOC/PU voltage need to be
at 1.25V for 396/792MHz setpoint, as 396M setpoint is
removed, so only increase 792M setpoint's voltage.Signed-off-by: Anson Huang
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When VPU freq is set to 352MHz, it needs to source clk
from PLL2_PFD2_396M, and PLL2_PFD2_396M need to change
freq to 352M, cpufreq's 396M setpoint will be removed.Busfreq will be disabled as it needs PLL2_PFD2 to be
as 396MHz to achieve low power audio freq setpoint.To enable VPU 352MHz feature, select it in menuconfig,
it is disabled by default.Signed-off-by: Anson Huang
Conflicts:
arch/arm/mach-imx/clk-imx6q.c
arch/arm/mach-imx/mach-imx6q.c -
Add busfreq support for i.MX6Q/DL, 3 setpoints supported:
HIGH: MMDC = 528MHz on i.MX6Q, = 396MHz on i.MX6DL; AHB = AXI = 24MHz;
AUDIO: MMDC = 50MHz, AXI = 50MHz, AHB = 25MHz;
LOW: MMDC = AXI = AHB = 24MHz.Signed-off-by: Anson Huang
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Add busfreq support for i.MX6Q/DL.
Signed-off-by: Anson Huang
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this patch adds A9-M4 power management, including
below features:1. busfreq: M4 is registered as a high speed device
of A9, when M4 is running at high speed, busfreq
will NOT enter low bus mode, when M4 is entering
its low power idle, A9 will be able to enter low
bus mode according to its state machine;
2. low power idle: only when M4 is in its low power
idle, busfreq is staying at low bus mode, low
power idle is available for kernel;
3. suspend: when M4 is NOT in its low power idle,
when linux is about to suspend, it will only
force SOC enter WAIT mode, only when M4 is in
its low power idle in TCM, linux suspend can
enter DSM mode. M4 can request/release wakeup
source via MU to A9.as M4 can NOT switch its clk parent due to glitch MUX,
to handle this case, A9 will help switch M4's clk
parent, the flow is as below:M4:
1. enter low power idle, send bus use count-- to A9;
2. enter wfi and only wait for MU interrupt;
3. receive A9's clk switch ready message, go into low
power idle;
4. receive interrupt to exit low power idle, send request
to A9 for increase busfreq and M4 freq, enter wfi
and only wait for MU interrupt;
5. receive A9 ready message, go out of low power idle.A9:
1. when receive M4's message of entering low power idle,
wait M4 into wfi, hold M4 in wfi by hardware, gate
M4 clk, then switch M4's clk to OSC, ungate M4 clk,
send ready command to wake up M4 into low power idle;
2. when receive M4's message of exiting low power idle,
wait M4 into wfi, hold M4 in wfi by hardware, gate
M4 clk, then switch M4's clk to origin high clk,
ungate M4 clk, send ready command to wake up M4
to exit low power idle;Signed-off-by: Anson Huang
Conflicts:
arch/arm/mach-imx/busfreq-imx6.c
arch/arm/mach-imx/pm-imx6.c