27 May, 2020
1 commit
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Add "fsl,spi-only-use-cs1-sel" to fit i.MX8DXL-EVK.
Spi common code does not support use of CS signals discontinuously.
It only uses CS1 without using CS0. So, add this property to re-config
chipselect value.Signed-off-by: Clark Wang
Reviewed-by: Fugang Duan
16 May, 2020
1 commit
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Add USB PHY tuning of imx8mq/p for USB certification, mainly for eye
diagram test.Reviewed-by: Peter Chen
Signed-off-by: Li Jun
22 Apr, 2020
1 commit
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The V2X MU requires that the the sender changes the byte indication
the type of the message in its header. The value required changes
for each MU.This patch adds the documentation of this functionality adding
explanations for fsl,cmd_tag and fsl,rsp_tag.Signed-off-by: Stéphane Dion
10 Apr, 2020
1 commit
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DPU found in i.MX8qxp SoC may drive a parallel display through
pixel link to LCDIF mux. This patch adds the device tree binding
documentation for LCDIF mux display.Reviewed-by: Robert Chiras
Tested-by: Robert Chiras
Signed-off-by: Liu Ying
09 Apr, 2020
2 commits
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Support i.MX8/8M/7ULP:
- Introduce early-booted property for M4 booted before Linux
- Introduce mboxes for rpmsg/virtio to communicate with M4
- Introduce mub-partition for hardware partition supported by i.MX8
- Introduce rsrc-table which hold the resource table
- Introduce rsrc-daReviewed-by: Richard Zhu
Signed-off-by: Peng Fan -
Convert the i.MX remoteproc binding to DT schema format
using json-schemaReviewed-by: Richard Zhu
Signed-off-by: Peng Fan
31 Mar, 2020
2 commits
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For dwc3-imx8mp, the clock for its power domain hsiomix has
to be handled by user, so add the hsio root clock to dwc3 imx8mp
binding doc.Reviewed-by: Peter Chen
Signed-off-by: Li Jun -
Document newly supported device tree properties max-cs to specify the
maximum cs the board supports.Signed-off-by: Han Xu
26 Mar, 2020
1 commit
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Some power domain need to be runtime always on to keep
the peripherals's weekup ability, for such power domain,
add the 'GENPD_FLAG_RPM_ALWAYS_ON' flag.Signed-off-by: Jacky Bai
Reviewed-by: Anson Huang
18 Mar, 2020
2 commits
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The phy registers are accessible after APB clock is enabled.
So, add the relevant clock properties in device tree doc.Reviewed-by: Sandor Yu
Signed-off-by: Liu Ying -
Add the active wakeup flag if a power domain has such requirement.
Signed-off-by: Jacky Bai
Reviewed-by: Anson Huang
14 Mar, 2020
1 commit
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Add the documentation for fsl,imx-secvio-sc binding.
Signed-off-by: Franck LENORMAND
12 Mar, 2020
2 commits
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Signed-off-by: Franck LENORMAND
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i.MX8/8X SECO MU is dedicated for communication between kernel
and SECO. To use SECO MU more effectivly, add "fsl,imx8-seco-mu"
compatible to support fast IPC.Signed-off-by: Peng Fan
Signed-off-by: Franck LENORMAND
08 Mar, 2020
1 commit
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Merge Linux stable release v5.4.24 into imx_5.4.y
* tag 'v5.4.24': (3306 commits)
Linux 5.4.24
blktrace: Protect q->blk_trace with RCU
kvm: nVMX: VMWRITE checks unsupported field before read-only field
...Signed-off-by: Jason Liu
Conflicts:
arch/arm/boot/dts/imx6sll-evk.dts
arch/arm/boot/dts/imx7ulp.dtsi
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
drivers/clk/imx/clk-composite-8m.c
drivers/gpio/gpio-mxc.c
drivers/irqchip/Kconfig
drivers/mmc/host/sdhci-of-esdhc.c
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
drivers/net/can/flexcan.c
drivers/net/ethernet/freescale/dpaa/dpaa_eth.c
drivers/net/ethernet/mscc/ocelot.c
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
drivers/net/phy/realtek.c
drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
drivers/perf/fsl_imx8_ddr_perf.c
drivers/tee/optee/shm_pool.c
drivers/usb/cdns3/gadget.c
kernel/sched/cpufreq.c
net/core/xdp.c
sound/soc/fsl/fsl_esai.c
sound/soc/fsl/fsl_sai.c
sound/soc/sof/core.c
sound/soc/sof/imx/Kconfig
sound/soc/sof/loader.c
04 Mar, 2020
2 commits
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Add driver support for i.MX8DXL DB Perf, which supports AXI ID PORT
CHANNEL filter.Reviewed-by: Fugang Duan
Signed-off-by: Joakim Zhang -
Add driver support for i.MX8DXL DDR Perf, which supports AXI ID PORT
CHANNEL filter.Reviewed-by: Fugang Duan
Signed-off-by: Joakim Zhang
26 Feb, 2020
2 commits
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Add documentation for a new clock 'phy_parent'. This clock is optional
and is used to re-parent the PHY related clocks (phy_ref, tx_esc and
rx_esc) to a valid parent. This clock is needed, in order to make the
re-parenting in driver, since the default re-parenting in dts node
(using assigned-clock-parents) may break the LVDS block, which has it's
PHY shared with MIPI-DSI.Signed-off-by: Robert Chiras
Signed-off-by: Dong Aisheng
(cherry picked from commit 7ed3b8738e3103396a5f3a9268c66f11f78cab03) -
QORIQ LS1028A soc used fsl,vf610-edma, but it has a little bit different
from others, so add new compatible to distinguish them.Signed-off-by: Peng Ma
Link: https://lore.kernel.org/r/20191212033714.4090-3-peng.ma@nxp.com
Signed-off-by: Vinod Koul
(cherry picked from commit f8dd1f395d1fbba049900ed48c09d76df49be712)
21 Feb, 2020
1 commit
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Signed-off-by: Franck LENORMAND
(cherry picked from commit f23aa19e875f7ca786c50116ad1b4b7c04625628)
18 Feb, 2020
2 commits
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Add "mem" clock that is required for imx8dxl platform.
Reviewed-by: Richard Zhu
Signed-off-by: Fugang Duan -
Add information for i.MX8MP DDRC which reports the single bit errors
that are corrected and the double bit errors that are detected.Signed-off-by: Sherry Sun
16 Feb, 2020
1 commit
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Add two parameters which are used to tune USB signal for imx picophy,
picophy is used at imx7d and imx8mm.Reviewed-by: Jun Li
Signed-off-by: Peter Chen
15 Feb, 2020
1 commit
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commit a6c4f77cb3b11f81077b53c4a38f21b92d41f21e upstream.
This patch set the correct value for oversampling maxItems. In the
original example, appears 3 items for oversampling while the maxItems
is set to 1, this patch fixes those issues.Fixes: 416f882c3b40 ("dt-bindings: iio: adc: Migrate AD7606 documentation to yaml")
Signed-off-by: Beniamin Bia
Signed-off-by: Rob Herring
Signed-off-by: Greg Kroah-Hartman
13 Feb, 2020
5 commits
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Add devicetree bindings for i.MX8mp LDB controller.
The controller supports two four data lane LVDS channels and supports
single/dual channel mode. The controller connects with LCDIFv3 on
i.MX8mp SoC.Reviewed-by: Sandor Yu
Signed-off-by: Liu Ying -
Add devicetree bindings for Freescale i.MX8mp LVDS PHY.
The IP block contains two PHYs, each of which supports
a four data lane LVDS channel.Reviewed-by: Sandor Yu
Signed-off-by: Liu Ying -
Add one standalone PCIe PHY for iMX8MP PCIe.
Signed-off-by: Richard Zhu
Reviewed-by: Fugang Duan -
Add one hsio phandle and compatible ID required by iMX8MP PCIe.
Signed-off-by: Richard Zhu
Reviewed-by: Fugang Duan -
Expand the gpr syscon compatible.
Signed-off-by: Richard Zhu
Reviewed-by: Fugang Duan
11 Feb, 2020
2 commits
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Add binding document.
Signed-off-by: Shengjiu Wang
Reviewed-by: Viorel Suman -
Add new property to support RMII external refclk.
Reviewed-by: Richard Zhu
Signed-off-by: Fugang Duan
29 Jan, 2020
1 commit
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Add "clock" property (and corresponding "clock-names")
for the CAAM SNVS node.This property is optional: there are cases when SNVS clock is kept
always on (chips such as i.MX6 SX, UL).
A good guide line is to check whether i.MX clk driver defines the clock.Signed-off-by: Horia Geantă
Reviewed-by: Iuliana Prodan
26 Jan, 2020
1 commit
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[ Upstream commit 0c0ef9ea6f3f0d5979dc7b094b0a184c1a94716b ]
Commit 0ed266d7ae5e ("clk: ti: omap3: cleanup unnecessary clock aliases")
removed old omap3 clock framework aliases but caused omap3-rom-rng to
stop working with clock not found error.Based on discussions on the mailing list it was requested by Tero Kristo
that it would be best to fix this issue by probing omap3-rom-rng using
device tree to provide a proper clk property. The other option would be
to add back the missing clock alias, but that does not help moving things
forward with removing old legacy platform_data.Let's also add a proper device tree binding and keep it together with
the fix.Cc: devicetree@vger.kernel.org
Cc: Aaro Koskinen
Cc: Adam Ford
Cc: Pali Rohár
Cc: Rob Herring
Cc: Sebastian Reichel
Cc: Tero Kristo
Fixes: 0ed266d7ae5e ("clk: ti: omap3: cleanup unnecessary clock aliases")
Reported-by: Aaro Koskinen
Signed-off-by: Tony Lindgren
Acked-by: Rob Herring
Signed-off-by: Herbert Xu
Signed-off-by: Sasha Levin
23 Jan, 2020
1 commit
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commit dbce0b65046d1735d7054c54ec2387dba84ba258 upstream.
DT property definitions must be under a 'properties' keyword. This was
missing for 'snps,tso' in an if/then clause. A meta-schema fix will
catch future errors like this.Fixes: 7db3545aef5f ("dt-bindings: net: stmmac: Convert the binding to a schemas")
Cc: "David S. Miller"
Acked-by: Maxime Ripard
Signed-off-by: Rob Herring
Signed-off-by: Greg Kroah-Hartman
21 Jan, 2020
1 commit
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Update the binding info for i.MX8MP TMU module.
Signed-off-by: Jacky Bai
Reviewed-by: Anson Huang
18 Jan, 2020
2 commits
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commit 7cf2804775f8a388411624b3e768e55d08711e9d upstream.
Headset codec is optional. Add missing update to DT binding document.
Fixes: a962a809e5e4 ("ASoC: mediatek: mt8183: make headset codec optional")
Signed-off-by: Tzung-Bi Shih
Link: https://lore.kernel.org/r/20190920112320.166052-1-tzungbi@google.com
Signed-off-by: Mark Brown
Signed-off-by: Greg Kroah-Hartman -
commit 392a9f63058f2cdcec8363b849a25532ee40da9f upstream.
The reset controller has a #reset-cells value of 1, so we should see a
phandle plus a register identifier, fix the example.Fixes: 0807caf647dd ("dt-bindings: reset: Add document for Broadcom STB reset controller")
Signed-off-by: Florian Fainelli
Signed-off-by: Philipp Zabel
Signed-off-by: Greg Kroah-Hartman
15 Jan, 2020
3 commits
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Adds compatible string for "nxp,cbtl04gp", which is also super speed
mux switch for type-c orientation, controlled by one GPIO.Reviewed-by: Peter Chen
Signed-off-by: Li Jun -
imx8mp SoC has the similar USB3 PHY with different version than
imx8mq, add compatible string "fsl,imx8mp-usb-phy", which has
the same properties.Reviewed-by: Peter Chen
Signed-off-by: Li Jun -
iMX8MP USB3 integrate Synopsys DesignWare Cores SuperSpeed
USB 3.0 Controller 3.30b IP, the glue layer is added to support
wakeup from low power mode.Reviewed-by: Peter Chen
Signed-off-by: Li Jun