Eric Lee / smarc-fsl-linux-kernel

16 Apr, 2020

1 commit

  • b4203ce05   i3c master: GETMRL's 3rd byte is optional even with BCR_IBI_PAYLOAD ... Browse Code »

    According to the I3C spec v1.1 document, GETMRL's payload is 2 bytes,
    with an optional 3rd byte if the IBI private payload is larger than
    1 byte. The whole GETMRL may also be optional so max_ibi_len already
    defaults to 1 if BCR_IBI_PAYLOAD prior to the i3c_master_getmrl_locked()
    call.

    Signed-off-by: Nicolas Pitre
    Signed-off-by: Boris Brezillon
    Link: https://lore.kernel.org/linux-i3c/nycvar.YSQ.7.76.2004151623060.2671@knanqh.ubzr

    Nicolas Pitre
     

29 Mar, 2020

1 commit

28 Feb, 2020

1 commit

27 Feb, 2020

1 commit

  • 12e21a23c   i3c: Fix MODALIAS uevents ... Browse Code »

    file2alias uses %X formatters. Fix typos in the MODALIAS uevent to print
    the part and ext IDs in uppercase.

    Signed-off-by: Boris Brezillon
    Signed-off-by: Vitor Soares
    Link: https://lore.kernel.org/linux-i3c/9ac5f1f8413fbb0481de76b5e43f2f4e1b2dc49f.1582796652.git.vitor.soares@synopsys.com

    Boris Brezillon
     

18 Feb, 2020

1 commit

09 Dec, 2019

1 commit

31 Oct, 2019

1 commit

01 Oct, 2019

1 commit

27 Aug, 2019

1 commit

12 Aug, 2019

1 commit

  • 7afe9a4e5   i3c: master: fix a memory leak bug ... Browse Code »

    In i3c_master_getmwl_locked(), the buffer used for the dest payload data is
    allocated using kzalloc() in i3c_ccc_cmd_dest_init(). Later on, the length
    of the dest payload data is checked against 'sizeof(*mwl)'. If they are not
    equal, -EIO is returned to indicate the error. However, the allocated
    buffer is not deallocated on this path, leading to a memory leak.

    To fix the above issue, free the buffer before returning the error.

    Signed-off-by: Wenwen Wang
    Signed-off-by: Boris Brezillon

    Wenwen Wang
     

11 Aug, 2019

2 commits

  • b1ac3a4b9   i3c: add addr and lvr to i2c_dev_desc structure ... Browse Code »

    I need to store address and lvr value for I2C devices without static definition
    in DT. This allows secondary master to transmit DEFSLVS command properly.

    Main changes between v4 and v5:
    - Change in defslvs to use addr and lvr from i2c_dev_desc structure
    - Change in CDNS and DW drivers to use addr and lvr from i2c_dev_desc structure

    Signed-off-by: Przemyslaw Gaj
    Signed-off-by: Boris Brezillon

    Przemyslaw Gaj
     
  • 91227632f   i3c: master: Add of_node_put() before return ... Browse Code »

    Each iteration of for_each_available_childe_of_node puts the previous
    node, but in the case of a return from the middle of the loop, there
    is no put, thus causing a memory leak. Add an of_node_put before the
    return.
    Issue found with Coccinelle.

    Signed-off-by: Nishka Dasgupta
    Signed-off-by: Boris Brezillon

    Nishka Dasgupta
     

27 Jul, 2019

1 commit

04 Jul, 2019

1 commit

  • ede200156   i3c: master: Use struct_size() helper ... Browse Code »

    Make use of the struct_size() helper instead of an open-coded version
    in order to avoid any potential type mistakes, in particular in the
    context in which this code is being used.

    So, replace the following form:

    sizeof(*defslvs) + ((ndevs - 1) * sizeof(struct i3c_ccc_dev_desc))

    with:

    struct_size(defslvs, slaves, ndevs - 1)

    This code was detected with the help of Coccinelle.

    Signed-off-by: Gustavo A. R. Silva
    Signed-off-by: Boris Brezillon

    Gustavo A. R. Silva
     

20 Jun, 2019

2 commits

  • cbf4f7325   i3c: add mixed limited bus mode ... Browse Code »

    The i3c bus spec defines a bus configuration where i2c devices don't
    have a 50ns filter but support SCL running at SDR max rate (12.5MHz).

    This patch introduces the limited bus mode so that users can use
    a higher speed in presence of i2c devices index 1.

    Signed-off-by: Vitor Soares
    Cc: Boris Brezillon
    Cc:
    Signed-off-by: Boris Brezillon

    Vitor Soares
     
  • ecc8fb54b   i3c: fix i2c and i3c scl rate by bus mode ... Browse Code »

    Currently the I3C framework limits SCL frequency to FM speed when
    dealing with a mixed slow bus, even if all I2C devices are FM+ capable.

    The core was also not accounting for I3C speed limitations when
    operating in mixed slow mode and was erroneously using FM+ speed as the
    max I2C speed when operating in mixed fast mode.

    Fixes: 3a379bbcea0a ("i3c: Add core I3C infrastructure")
    Signed-off-by: Vitor Soares
    Cc: Boris Brezillon
    Cc:
    Cc:
    Signed-off-by: Boris Brezillon

    Vitor Soares
     

28 May, 2019

1 commit

  • 88c503224   i3c: Drop support for I2C 10 bit addresing ... Browse Code »

    This patch drops support for I2C devices with 10 bit addressing. When I2C
    device with 10 bit address is defined in DT, I3C master registration fails.

    Address space for I2C devices has been reduced and ->i2c_funcs() hook has been
    removed.

    Because this patch series dropped support for 10 bit I2C devices, support is
    also dropped in Cadence I3C master driver and Synopsys DesignWare I3C master
    driver.

    Signed-off-by: Przemyslaw Gaj
    Signed-off-by: Boris Brezillon

    Przemyslaw Gaj
     

07 May, 2019

1 commit

06 May, 2019

1 commit

  • 476c7e1d3   i3c: Fix a shift wrap bug in i3c_bus_set_addr_slot_status() ... Browse Code »

    The problem here is that addr can be I3C_BROADCAST_ADDR (126). That
    means we're shifting by (126 * 2) % 64 which is 60. The
    I3C_ADDR_SLOT_STATUS_MASK is an enum which is an unsigned int in GCC
    so shifts greater than 31 are undefined.

    Fixes: 3a379bbcea0a ("i3c: Add core I3C infrastructure")
    Cc:
    Signed-off-by: Dan Carpenter
    Signed-off-by: Boris Brezillon

    Dan Carpenter
     

10 Apr, 2019

1 commit

  • 9752c37cc   i3c: Fix the verification of random PID ... Browse Code »

    The validation of random PID should be done by checking the
    boardinfo->pid instead of info.pid which is empty.

    Doing the change the info struture declaration is no longer necessary.

    Cc: Boris Brezillon
    Cc:
    Fixes: 3a379bbcea0a ("i3c: Add core I3C infrastructure")
    Signed-off-by: Vitor Soares
    Signed-off-by: Boris Brezillon

    Vitor Soares
     

25 Jan, 2019

1 commit

06 Dec, 2018

2 commits

12 Nov, 2018

1 commit

  • 3a379bbce   i3c: Add core I3C infrastructure ... Browse Code »

    Add core infrastructure to support I3C in Linux and document it.

    This infrastructure adds basic I3C support. Advanced features will be
    added afterwards.

    There are a few design choices that are worth mentioning because they
    impact the way I3C device drivers can interact with their devices:

    - all functions used to send I3C/I2C frames must be called in
    non-atomic context. Mainly done this way to ease implementation, but
    this is not set in stone, and if anyone needs async support, new
    functions can be added later on.
    - the bus element is a separate object, but it's tightly coupled with
    the master object. We thus have a 1:1 relationship between i3c_bus
    and i3c_master_controller objects, and if 2 master controllers are
    connected to the same bus and both exposed to the same Linux instance
    they will appear as two distinct busses, and devices on this bus will
    be exposed twice.
    - I2C backward compatibility has been designed to be transparent to I2C
    drivers and the I2C subsystem. The I3C master just registers an I2C
    adapter which creates a new I2C bus. I'd say that, from a
    representation PoV it's not ideal because what should appear as a
    single I3C bus exposing I3C and I2C devices here appears as 2
    different buses connected to each other through the parenting (the
    I3C master is the parent of the I2C and I3C busses).
    On the other hand, I don't see a better solution if we want something
    that is not invasive.

    Missing features:
    - I3C HDR modes are not supported
    - no support for multi-master and the associated concepts (mastership
    handover, support for secondary masters, ...)
    - I2C devices can only be described using DT because this is the only
    use case I have. However, the framework can easily be extended with
    ACPI and board info support
    - I3C slave framework. This has been completely omitted, but shouldn't
    have a huge impact on the I3C framework because I3C slaves don't see
    the whole bus, it's only about handling master requests and generating
    IBIs. Some of the struct, constant and enum definitions could be
    shared, but most of the I3C slave framework logic will be different

    Signed-off-by: Boris Brezillon
    Reviewed-by: Arnd Bergmann
    Acked-by: Greg Kroah-Hartman

    Boris Brezillon