18 Oct, 2010
2 commits
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The end condition of for_each_frequency should care about
both clk_rate_table_round and clk_rate_div_range_round,
and using "correct max size" is a natural idea in later function.
To avoid data over flow, this patch didn't modify
clk_rate_div_range_round side as .max = div_max + 1.Signed-off-by: Kuninori Morimoto
Signed-off-by: Paul Mundt -
clk_get() returns an ERR_PTR(errno) on error and not NULL.
Signed-off-by: Guennadi Liakhovetski
Signed-off-by: Paul Mundt
15 Oct, 2010
7 commits
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When updating the iterator macro an old argument assignment was used on
the initial assignment causing a fault on the table rounding. Fix it up.Signed-off-by: Paul Mundt
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This adds a new clk_rate_div_range_round() for implementing rate rounding
by divisor ranges. This can be used trivially by clocks that support
arbitrary ranged divisors without the need for rate table construction.This should only be used by clocks that both have large divisor ranges in
addition to clocks that will never be arbitrarily scaled, as the lack of
a backing frequency table will prevent cpufreq from being able to do much
of anything with them.Primarily intended for use as a ->recalc helper.
Signed-off-by: Paul Mundt
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Presently the only assisted rate rounding is frequency table backed, but
there are cases where it's impractical to use a frequency table for
certain clocks (such as the FSIDIV case, which supports 65535 divisors),
and we wish to reuse the same rate rounding algorithm.This breaks out the core of the rate rounding logic in to its own helper
routine and shuffles the frequency table logic around, switching to using
an iterator for the generic helper routine.Signed-off-by: Paul Mundt
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This implements support for ioremapping of register windows that
encapsulate clock control registers used by a struct clk, with
transparent sibling inheritance.Root clocks at the top of a given topology often encapsulate the entire
register space of all of their sibling clocks, so this mapping can be
done once and handed down. A given clock enable/disable case maps out to
a single bit in a shared register, so this prevents creating multiple
overlapping mappings.The mapping case breaks down in to a couple of different situations:
- Sibling clocks without a specific mapping.
- Root clocks without a specific mapping.
- Any of sibling/root clocks with a specific mapping.Sibling clocks with no specified mapping will grovel up the clock chain
and install the root clock mapping unconditionally at registration time.Root clocks without their own mappings have a dummy BSS-initialized
mapping inserted that is handed down the chain just like any other
mapping. This permits all of the sibling clock ops to read/write using
the mapping offsets without any special configuration, enabling them to
not care whether access ultimately goes through translatable or
untranslatable memory.Any clock with its own mapping will have the window initialized at
registration time and be ready for use by its clock ops. Failure to
establish the mapping will prevent registration, so no additional sanity
checks are needed. Sibling clocks that double as parents for the moment
will not propagate their mapping down, but this is easily tunable if the
need arises.All clock mappings are kref refcounted, with each instance of mapping
inheritance incrementing the refcount.Tested-by: Kuninori Morimoto
Signed-off-by: Paul Mundt -
Instead of hand-rolling our own, just use the generic ones instead.
Signed-off-by: Paul Mundt
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This ties in the 2KiB of FPGA SRAM in to the generic SRAM pool.
Signed-off-by: Paul Mundt
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This sets up a generic SRAM pool for CPUs and platform code to insert
their otherwise unused memories into. A simple alloc/free interface is
provided (lifed from avr32) for generic code.This only applies to tiny SRAMs that are otherwise unmanaged, and does
not take in to account the more complex SRAMs sitting behind transfer
engines, or that employ an I/D split.Signed-off-by: Paul Mundt
14 Oct, 2010
4 commits
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The SDK7786 FPGA has secondary control over the PCIe clocks, specifically
relating to the slots and oscillator. This ties the FPGA clocks in to the
clock framework and balances the refcounting similar to how the primary
on-chip clocks are managed. While the on-chip clocks are per-port, the
FPGA clock enable/disable is global for the entire block.Signed-off-by: Paul Mundt
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SDK7786 supports connecting either slot3 or 4 to the same PCIe port by
way of FPGA muxing. By default the vertical slot 3 on the baseboard is
enabled, so this adds in a command line option for forcibly enabling the
slot 4 edge connector.If nothing has been specified on the command line, we fall back to
reading the resistor values for card presence to figure out where to
route the port to.Signed-off-by: Paul Mundt
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This first converts the PMB locking over to raw spinlocks, and secondly
fixes up a nested locking issue that was triggering lockdep early on:swapper/0 is trying to acquire lock:
(&pmbe->lock){......}, at: [] pmb_init+0xf4/0x4dcbut task is already holding lock:
(&pmbe->lock){......}, at: [] pmb_init+0xc6/0x4dcother info that might help us debug this:
1 lock held by swapper/0:
#0: (&pmbe->lock){......}, at: [] pmb_init+0xc6/0x4dcSigned-off-by: Paul Mundt
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The sdk7786 FPGA supports a number of user settable input switches that
are otherwise unused. This wires up a dummy gpio chip for the switch bank
to simply expose them to userspace.Signed-off-by: Paul Mundt
13 Oct, 2010
6 commits
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Signed-off-by: Paul Mundt
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Remove "name" and "id" from drivers/sh/ struct clk.
The struct clk members "name" and "id" are not used
now when matching is done through clkdev.Signed-off-by: Magnus Damm
Signed-off-by: Paul Mundt -
Without this fix the LCDC driver will try to free
framebuffer memory even though the allocation failed.Signed-off-by: Magnus Damm
Signed-off-by: Paul Mundt -
Presently this is uninitialized in the architecture code, so it's
artificlally capped to the default initialization value. Set it up at
registration time.Signed-off-by: Paul Mundt
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The PMCAT location has conveniently moved on newer SH-X3 parts, special
case this for now with a note. This will probably want to be redone in a
less visually offensive way when/if more information becomes available.Signed-off-by: Paul Mundt
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This plugs in the alignment and emulation fault reporting for perf sw
events.Signed-off-by: Paul Mundt
11 Oct, 2010
1 commit
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Checks for (irq < 0) and (ilsel < 0) didn't make sense since they were
unsigned. Made them signed.Signed-off-by: Vasiliy Kulikov
Signed-off-by: Paul Mundt
07 Oct, 2010
1 commit
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SH-3 lacks an MMUCR_TI definition for global TLB flushes. As SH-3 parts
lack a split TLB, the same global flush behaviour is accomplished
through the flush bit, which just happens to be the same as on SH-4.This fixes up the build for all SH-3 MMU parts.
Signed-off-by: Paul Mundt
06 Oct, 2010
4 commits
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Signed-off-by: Nobuhiro Iwamatsu
Signed-off-by: Paul Mundt -
The spinlock in traps_64.c is used without initialization.
This fixes it by declaring DEFINE_SPINLOCK() and makes the spinlock static
variable.Signed-off-by: Akinobu Mita
Cc: Paul Mundt
Cc: linux-sh@vger.kernel.org
Signed-off-by: Paul Mundt -
The balancing stubs obviously need to be static inline..
Signed-off-by: Paul Mundt
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The Kconfig and Makefile were overlooked, add those in now to improve
odds of building.Signed-off-by: Paul Mundt
05 Oct, 2010
5 commits
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SH7786 is the big user for subgroup splitting, mostly for the PCIe block,
but those will follow later. For now we simply split up SCIF1, as used by
the serial console on SDK7786 and others.Signed-off-by: Paul Mundt
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This splits up the sh intc core in to something more vaguely resembling
a subsystem. Most of the functionality was alread fairly well
compartmentalized, and there were only a handful of interdependencies
that needed to be resolved in the process.This also serves as future-proofing for the genirq and sparseirq rework,
which will make some of the split out functionality wholly generic,
allowing things to be killed off in place with minimal migration pain.Signed-off-by: Paul Mundt
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If lookups happen while the radix node still points to a subgroup
mapping, an IRQ hasn't yet been made available for the specified id, so
error out accordingly. Once the slot is replaced with an IRQ mapping and
the tag is discarded, lookup can commence as normal.Signed-off-by: Paul Mundt
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Many interrupts that share a single mask source but are on different
hardware vectors will have an associated register tied to an INTEVT that
denotes the precise cause for the interrupt exception being triggered.This introduces the concept of IRQ subgroups in the intc core, where
a virtual IRQ map is constructed for each of the pre-defined cause bits,
and a higher level chained handler takes control of the parent INTEVT.
This enables CPUs with heavily muxed IRQ vectors (especially across
disjoint blocks) to break things out in to a series of managed chained
handlers while being able to dynamically lookup and adopt the IRQs
created for them.This is largely an opt-in interface, requiring CPUs to manually submit
IRQs for subgroup splitting, in addition to providing identifiers in
their enum maps that can be used for lazy lookup via the radix tree.Signed-off-by: Paul Mundt
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This implements a scheme roughly analogous to the PowerPC virtual to
hardware IRQ mapping, which we use for IRQ to per-controller ID mapping.
This makes it possible for drivers to use the IDs directly for lookup
instead of hardcoding the vector.The main motivation for this work is as a building block for dynamically
allocating virtual IRQs for demuxing INTC events sharing a single INTEVT
in addition to a common masking source.Signed-off-by: Paul Mundt
04 Oct, 2010
7 commits
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The gpiolib debugfs entry takes a hammer approach and iterates over all
of the potential GPIOs, regardless of their type. The SH PFC code on the
other hand contains a variable mismash of input/output/function types
spread out sparsely, leading to situations where the debug code can
trigger an out of range enum for the type. Since we already have an error
path for out of range enums, we can just hand that up to the higher level
instead of the current BUG() behaviour.Signed-off-by: Paul Mundt
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The gpio sysfs support needs to get at these later, so drop the
__initdata annotations.Signed-off-by: Paul Mundt
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Presently the pinmux code is a one-way thing, but there's nothing
preventing an unregistration if no one has grabbed any of the pins.
This will permit us to save a bit of memory on systems that require pin
demux for certain peripherals in the case where registration of those
peripherals fails, or they are otherwise not attached to the system.Signed-off-by: Paul Mundt
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At the moment ILSEL blows up with a BUG when aliased sets are handed in,
but as the enable call is able to hand back errors we opt for that path
instead. None of the ILSEL peripherals are vital to the board's
operation, so trapping a BUG is a bit excessive.Signed-off-by: Paul Mundt
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This adds gpio-keys mappings for the button matrix on the baseboard,
now that we have support for the pin controller.Signed-off-by: Paul Mundt
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This adds trivial support for the GPIOs implemented through the baseboard
CPLD, used for driving the button matrix.Signed-off-by: Paul Mundt
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We'll be adding more headers for this board, so move this over to its own
directory.Signed-off-by: Paul Mundt
03 Oct, 2010
1 commit
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As non-PFC chips are added that may support IRQs, pass through to the
generic helper instead of triggering the WARN_ON().Signed-off-by: Paul Mundt
02 Oct, 2010
2 commits
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Some controllers will need to be initialized lazily due to pinmux
constraints, while others may simply have no need to be brought online if
there are no backing devices for them attached. In this case it's still
necessary to be able to reserve their hardware vector map before dynamic
IRQs get a hold of them.Signed-off-by: Paul Mundt
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The SH-X3 proto CPU has all of the external IRQ and IRL pins muxed, make
sure that we're able to grab them before attempting to register their
respective IRQ controllers.Signed-off-by: Paul Mundt