15 Aug, 2019
12 commits
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crypto/aes_generic.c:64:18: warning:
rco_tab defined but not used [-Wunused-const-variable=]It is never used, so can be removed.
Reported-by: Hulk Robot
Signed-off-by: YueHaibing
Acked-by: Ard Biesheuvel
Signed-off-by: Herbert Xu -
This fixes the following Sphinx warning:
Documentation/crypto/crypto_engine.rst:2:
WARNING: Explicit markup ends without a blank line; unexpected unindent.Signed-off-by: Jonathan Neuschäfer
Signed-off-by: Herbert Xu -
This patch configures and initializes CNN55XX device AQM hardware unit.
Signed-off-by: Phani Kiran Hemadri
Reviewed-by: Srikanth Jampala
Signed-off-by: Herbert Xu -
This patch adds support to allocate CNN55XX device AQMQ command queues
required for submitting asymmetric crypto requests.Signed-off-by: Phani Kiran Hemadri
Reviewed-by: Srikanth Jampala
Signed-off-by: Herbert Xu -
Reference counters are preferred to use refcount_t instead of
atomic_t.
This is because the implementation of refcount_t can prevent
overflows and detect possible use-after-free.
So convert atomic_t ref counters to refcount_t.Signed-off-by: Chuhong Yuan
Signed-off-by: Herbert Xu -
The hwrng_fill() function can run while devices are suspending and
resuming. If the hwrng is behind a bus such as i2c or SPI and that bus
is suspended, the hwrng may hang the bus while attempting to add some
randomness. It's been observed on ChromeOS devices with suspend-to-idle
(s2idle) and an i2c based hwrng that this kthread may run and ask the
hwrng device for randomness before the i2c bus has been resumed.Let's make this kthread freezable so that we don't try to touch the
hwrng during suspend/resume. This ensures that we can't cause the hwrng
backing driver to get into a bad state because the device is guaranteed
to be resumed before the hwrng kthread is thawed.Cc: Andrey Pronin
Cc: Duncan Laurie
Cc: Jason Gunthorpe
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Cc: Guenter Roeck
Cc: Alexander Steffen
Signed-off-by: Stephen Boyd
Signed-off-by: Herbert Xu -
In the process of turning caam/qi into a library, the check of
MCFGR[QI] bit has been inadvertently dropped.
Fix the condition for DPAA 1.x QI detection, which should be:
MCFGR[QI] && !MCFGR[DPAA2]A check in the library exit point is currently not needed,
since the list of registered algorithms is empty.While here, silence the library initialization abort - since jr.c
calls it unconditionally.Fixes: 1b46c90c8e00 ("crypto: caam - convert top level drivers to libraries")
Signed-off-by: Horia Geantă
Signed-off-by: Herbert Xu -
Directly return error in the first loop in hisi_zip_create_req_q.
Fixes: 62c455ca853e ("crypto: hisilicon - add HiSilicon ZIP accelerator support")
Signed-off-by: Zhou Wang
Signed-off-by: Herbert Xu -
Fix to add missing single_release in qm_regs_fops.
Fixes: 263c9959c937 ("crypto: hisilicon - add queue management driver for HiSilicon QM module")
Signed-off-by: Zhou Wang
Signed-off-by: Herbert Xu -
Just init curr_sgl_dma = 0 to avoid compile warning.
Fixes: dfed0098ab91 ("crypto: hisilicon - add hardware SGL support")
Reported-by: kbuild test robot
Signed-off-by: Zhou Wang
Signed-off-by: Herbert Xu -
Add ARM64/PCI/PCI_MSI dependency for CRYPTO_DEV_HISI_ZIP.
Fixes: 62c455ca853e ("crypto: hisilicon - add HiSilicon ZIP accelerator support")
Reported-by: kbuild test robot
Signed-off-by: Zhou Wang
Signed-off-by: Herbert Xu -
Fix to use proper type of argument for dma_addr_t and size_t.
Fixes: 263c9959c937 ("crypto: hisilicon - add queue management driver for HiSilicon QM module")
Reported-by: kbuild test robot
Signed-off-by: Zhou Wang
Signed-off-by: Herbert Xu
09 Aug, 2019
28 commits
-
Exercising CPU hotplug on a 5.2 kernel with recent padata fixes from
cryptodev-2.6.git in an 8-CPU kvm guest...# modprobe tcrypt alg="pcrypt(rfc4106(gcm(aes)))" type=3
# echo 0 > /sys/devices/system/cpu/cpu1/online
# echo c > /sys/kernel/pcrypt/pencrypt/parallel_cpumask
# modprobe tcrypt mode=215...caused the following crash:
BUG: kernel NULL pointer dereference, address: 0000000000000000
#PF: supervisor read access in kernel mode
#PF: error_code(0x0000) - not-present page
PGD 0 P4D 0
Oops: 0000 [#1] SMP PTI
CPU: 2 PID: 134 Comm: kworker/2:2 Not tainted 5.2.0-padata-base+ #7
Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.12.0-
Workqueue: pencrypt padata_parallel_worker
RIP: 0010:padata_reorder+0xcb/0x180
...
Call Trace:
padata_do_serial+0x57/0x60
pcrypt_aead_enc+0x3a/0x50 [pcrypt]
padata_parallel_worker+0x9b/0xe0
process_one_work+0x1b5/0x3f0
worker_thread+0x4a/0x3c0
...In padata_alloc_pd, pd->cpu is set using the user-supplied cpumask
instead of the effective cpumask, and in this case cpumask_first picked
an offline CPU.The offline CPU's reorder->list.next is NULL in padata_reorder because
the list wasn't initialized in padata_init_pqueues, which only operates
on CPUs in the effective mask.Fix by using the effective mask in padata_alloc_pd.
Fixes: 6fc4dbcf0276 ("padata: Replace delayed timer with immediate workqueue in padata_reorder")
Signed-off-by: Daniel Jordan
Cc: Herbert Xu
Cc: Steffen Klassert
Cc: linux-crypto@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Herbert Xu -
Remove unused includes of linux/pci.h.
Signed-off-by: Bjorn Helgaas
Acked-by: Gary R Hook
Signed-off-by: Herbert Xu -
ccp-dev.h uses dma_direction, which is defined in linux/dma-direction.h.
Include that explicitly instead of relying on it being included via
linux/pci.h, since ccp-dev.h requires nothing else from linux/pci.h.Similarly, ccp-dmaengine.c uses dma_get_mask(), which is defined in
linux/dma-mapping.h, so include that explicitly since it requires nothing
else from linux/pci.h.A future patch will remove the includes of linux/pci.h where it is not
needed.Signed-off-by: Bjorn Helgaas
Acked-by: Gary R Hook
Signed-off-by: Herbert Xu -
Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.Reported-by: Hulk Robot
Signed-off-by: YueHaibing
Signed-off-by: Herbert Xu -
Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.Reported-by: Hulk Robot
Signed-off-by: YueHaibing
Signed-off-by: Herbert Xu -
Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.Reported-by: Hulk Robot
Signed-off-by: YueHaibing
Signed-off-by: Herbert Xu -
Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.Reported-by: Hulk Robot
Signed-off-by: YueHaibing
Reviewed-by: Heiko Stuebner
Signed-off-by: Herbert Xu -
Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.Reported-by: Hulk Robot
Signed-off-by: YueHaibing
Signed-off-by: Herbert Xu -
Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.Reported-by: Hulk Robot
Signed-off-by: YueHaibing
Acked-by: Jamie Iles
Signed-off-by: Herbert Xu -
Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.Reported-by: Hulk Robot
Signed-off-by: YueHaibing
Signed-off-by: Herbert Xu -
Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.Reported-by: Hulk Robot
Signed-off-by: YueHaibing
Acked-by: Antoine Tenart
Signed-off-by: Herbert Xu -
Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.Reported-by: Hulk Robot
Signed-off-by: YueHaibing
Signed-off-by: Herbert Xu -
Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.Reported-by: Hulk Robot
Signed-off-by: YueHaibing
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Herbert Xu -
Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.Reported-by: Hulk Robot
Signed-off-by: YueHaibing
Signed-off-by: Herbert Xu -
Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.Reported-by: Hulk Robot
Signed-off-by: YueHaibing
Signed-off-by: Herbert Xu -
Based on seqiv, IPsec ESP and rfc4543/rfc4106 the assoclen can be 16 or
20 bytes.From esp4/esp6, assoclen is sizeof IP Header. This includes spi, seq_no
and extended seq_no, that is 8 or 12 bytes.
In seqiv, to asscolen is added the IV size (8 bytes).
Therefore, the assoclen, for rfc4543, should be restricted to 16 or 20
bytes, as for rfc4106.Signed-off-by: Iuliana Prodan
Reviewed-by: Horia Geanta
Signed-off-by: Herbert Xu -
Add Zhou Wang as a maintainer for HiSilicon QM and ZIP controller driver.
Signed-off-by: Zhou Wang
Reviewed-by: John Garry
Signed-off-by: Herbert Xu -
HiSilicon ZIP engine driver uses debugfs to provide debug information,
the usage can be found in /Documentation/ABI/testing/debugfs-hisi-zip.Signed-off-by: Zhou Wang
Signed-off-by: Herbert Xu -
Add debugfs descriptions for HiSilicon ZIP and QM driver.
Signed-off-by: Zhou Wang
Reviewed-by: Jonathan Cameron
Signed-off-by: Herbert Xu -
HiSilicon ZIP engine supports PCI SRIOV. This patch enable this feature.
User can enable VFs and pass through them to VM, same ZIP driver can work
in VM to provide ZLIB and GZIP algorithm by crypto acomp interface.Signed-off-by: Zhou Wang
Signed-off-by: Herbert Xu -
The HiSilicon ZIP accelerator implements the zlib and gzip algorithm. It
uses Hisilicon QM as the interface to the CPU.This patch provides PCIe driver to the accelerator and registers it to
crypto acomp interface. It also uses sgl as data input/output interface.Signed-off-by: Zhou Wang
Signed-off-by: Shiju Jose
Signed-off-by: Kenneth Lee
Signed-off-by: Hao Fang
Reviewed-by: Jonathan Cameron
Reviewed-by: John Garry
Signed-off-by: Herbert Xu -
HiSilicon accelerators in Hip08 use same hardware scatterlist for data format.
We support it in this module.Specific accelerator drivers can use hisi_acc_create_sgl_pool to allocate
hardware SGLs ahead. Then use hisi_acc_sg_buf_map_to_hw_sgl to get one
hardware SGL and pass related information to hardware SGL.The DMA address of mapped hardware SGL can be passed to SGL src/dst field
in QM SQE.Signed-off-by: Zhou Wang
Signed-off-by: Herbert Xu -
QM is a general IP used by HiSilicon accelerators. It provides a general
PCIe interface for the CPU and the accelerator to share a group of queues.A QM integrated in an accelerator provides queue management service.
Queues can be assigned to PF and VFs, and queues can be controlled by
unified mailboxes and doorbells. Specific task request are descripted by
specific description buffer, which will be controlled and pass to related
accelerator IP by QM.This patch adds a QM driver used by the accelerator driver to access
the QM hardware.Signed-off-by: Zhou Wang
Signed-off-by: Kenneth Lee
Signed-off-by: Shiju Jose
Signed-off-by: Hao Fang
Reviewed-by: Jonathan Cameron
Reviewed-by: John Garry
Signed-off-by: Herbert Xu -
The crypto engine initializes its kworker thread to FIFO-99 (when
requesting RT priority), reduce this to FIFO-50.FIFO-99 is the very highest priority available to SCHED_FIFO and
it not a suitable default; it would indicate the crypto work is the
most important work on the machine.Cc: Herbert Xu
Cc: "David S. Miller"
Cc: linux-crypto@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: Thomas Gleixner
Signed-off-by: Peter Zijlstra (Intel)
Signed-off-by: Herbert Xu -
To be consistent with other CAAM modules, caamhash should return 0
instead of -ENODEV in case CAAM has no MDHA.Based on commit 1b46c90c8e00 ("crypto: caam - convert top level drivers to libraries")
the value returned by entry point is never checked and
the exit point is always executed.Signed-off-by: Iuliana Prodan
Reviewed-by: Horia Geanta
Signed-off-by: Herbert Xu -
To know if a registration succeeded added a new struct,
caam_akcipher_alg, that keeps, also, the registration status.
This status is updated in caam_pkc_init and verified in
caam_pkc_exit to unregister an algorithm.Fixes: 1b46c90c8e00 ("crypto: caam - convert top level drivers to libraries")
Signed-off-by: Iuliana Prodan
Reviewed-by: Horia Geanta
Signed-off-by: Herbert Xu -
Commit 1b46c90c8e00 ("crypto: caam - convert top level drivers to libraries")
changed entry and exit points behavior for caamalg,
caamalg_qi, caamalg_qi2, caamhash, caampkc, caamrng.For example, previously caam_pkc_init() and caam_pkc_exit() were
module entry/exit points. This means that if an error would happen
in caam_pkc_init(), then caam_pkc_exit() wouldn't have been called.
After the mentioned commit, caam_pkc_init() and caam_pkc_exit()
are manually called - from jr.c. caam_pkc_exit() is called
unconditionally, even if caam_pkc_init() failed.Added a global variable to keep the status of the algorithm
registration and free of resources.
The exit point of caampkc/caamrng module is executed only if the
registration was successful. Therefore we avoid double free of
resources in case the algorithm registration failed.Fixes: 1b46c90c8e00 ("crypto: caam - convert top level drivers to libraries")
Signed-off-by: Iuliana Prodan
Reviewed-by: Horia Geanta
Signed-off-by: Herbert Xu -
Check the return value of the hardware registration for caam_rng and free
resources in case of failure.Fixes: e24f7c9e87d4 ("crypto: caam - hwrng support")
Signed-off-by: Iuliana Prodan
Reviewed-by: Horia Geanta
Signed-off-by: Herbert Xu
