Eric Lee / smarc-fsl-linux-kernel

15 Jun, 2022

1 commit

  • 604e35f70   clocksource/drivers/riscv: Events are stopped during CPU suspend ... Browse Code »

    [ Upstream commit 232ccac1bd9b5bfe73895f527c08623e7fa0752d ]

    Some implementations of the SBI time extension depend on hart-local
    state (for example, CSRs) that are lost or hardware that is powered
    down when a CPU is suspended. To be safe, the clockevents driver
    cannot assume that timer IRQs will be received during CPU suspend.

    Fixes: 62b019436814 ("clocksource: new RISC-V SBI timer driver")
    Signed-off-by: Samuel Holland
    Reviewed-by: Anup Patel
    Link: https://lore.kernel.org/r/20220509012121.40031-1-samuel@sholland.org
    Signed-off-by: Daniel Lezcano
    Signed-off-by: Sasha Levin

    Samuel Holland
     

21 Aug, 2020

1 commit

  • 2bc3fc877   RISC-V: Remove CLINT related code from timer and arch ... Browse Code »

    Right now the RISC-V timer driver is convoluted to support:
    1. Linux RISC-V S-mode (with MMU) where it will use TIME CSR for
    clocksource and SBI timer calls for clockevent device.
    2. Linux RISC-V M-mode (without MMU) where it will use CLINT MMIO
    counter register for clocksource and CLINT MMIO compare register
    for clockevent device.

    We now have a separate CLINT timer driver which also provide CLINT
    based IPI operations so let's remove CLINT MMIO related code from
    arch/riscv directory and RISC-V timer driver.

    Signed-off-by: Anup Patel
    Tested-by: Emil Renner Berhing
    Acked-by: Daniel Lezcano
    Reviewed-by: Atish Patra
    Reviewed-by: Palmer Dabbelt
    Signed-off-by: Palmer Dabbelt

    Anup Patel
     

10 Jun, 2020

1 commit

  • 033a65de7   clocksource/drivers/timer-riscv: Use per-CPU timer interrupt ... Browse Code »

    Instead of directly calling RISC-V timer interrupt handler from
    RISC-V local interrupt conntroller driver, this patch implements
    RISC-V timer interrupt as a per-CPU interrupt using per-CPU APIs
    of Linux IRQ subsystem.

    Signed-off-by: Anup Patel
    Reviewed-by: Atish Patra
    Reviewed-by: Marc Zyngier
    Signed-off-by: Palmer Dabbelt

    Anup Patel
     

05 Jan, 2020

1 commit

  • 9d05c18e8   clocksource: riscv: add notrace to riscv_sched_clock ... Browse Code »

    When enabling ftrace graph tracer, it gets the tracing clock in
    ftrace_push_return_trace(). Eventually, it invokes riscv_sched_clock()
    to get the clock value. If riscv_sched_clock() isn't marked with
    'notrace', it will call ftrace_push_return_trace() and cause infinite
    loop.

    The result of failure as follow:

    command: echo function_graph >current_tracer
    [ 46.176787] Unable to handle kernel paging request at virtual address ffffffe04fb38c48
    [ 46.177309] Oops [#1]
    [ 46.177478] Modules linked in:
    [ 46.177770] CPU: 0 PID: 256 Comm: $d Not tainted 5.5.0-rc1 #47
    [ 46.177981] epc: ffffffe00035e59a ra : ffffffe00035e57e sp : ffffffe03a7569b0
    [ 46.178216] gp : ffffffe000d29b90 tp : ffffffe03a756180 t0 : ffffffe03a756968
    [ 46.178430] t1 : ffffffe00087f408 t2 : ffffffe03a7569a0 s0 : ffffffe03a7569f0
    [ 46.178643] s1 : ffffffe00087f408 a0 : 0000000ac054cda4 a1 : 000000000087f411
    [ 46.178856] a2 : 0000000ac054cda4 a3 : 0000000000373ca0 a4 : ffffffe04fb38c48
    [ 46.179099] a5 : 00000000153e22a8 a6 : 00000000005522ff a7 : 0000000000000005
    [ 46.179338] s2 : ffffffe03a756a90 s3 : ffffffe00032811c s4 : ffffffe03a756a58
    [ 46.179570] s5 : ffffffe000d29fe0 s6 : 0000000000000001 s7 : 0000000000000003
    [ 46.179809] s8 : 0000000000000003 s9 : 0000000000000002 s10: 0000000000000004
    [ 46.180053] s11: 0000000000000000 t3 : 0000003fc815749c t4 : 00000000000efc90
    [ 46.180293] t5 : ffffffe000d29658 t6 : 0000000000040000
    [ 46.180482] status: 0000000000000100 badaddr: ffffffe04fb38c48 cause: 000000000000000f

    Signed-off-by: Zong Li
    Reviewed-by: Steven Rostedt (VMware)
    [paul.walmsley@sifive.com: cleaned up patch description]
    Fixes: 92e0d143fdef ("clocksource/drivers/riscv_timer: Provide the sched_clock")
    Cc: stable@vger.kernel.org
    Signed-off-by: Paul Walmsley

    Zong Li
     

14 Nov, 2019

1 commit

  • 4f9bbcefa   riscv: add support for MMIO access to the timer registers ... Browse Code »

    When running in M-mode we can't use the SBI to set the timer, and
    don't have access to the time CSR as that usually is emulated by
    M-mode. Instead provide code that directly accesses the MMIO for
    the timer.

    Signed-off-by: Christoph Hellwig
    Reviewed-by: Anup Patel
    Acked-by: Thomas Gleixner # for drivers/clocksource
    [paul.walmsley@sifive.com: updated to apply; fixed checkpatch
    issue; timex.h now includes asm/mmio.h to resolve header file
    problems]
    Signed-off-by: Paul Walmsley

    Christoph Hellwig
     

06 Nov, 2019

1 commit

  • a4c3733d3   riscv: abstract out CSR names for supervisor vs machine mode ... Browse Code »

    Many of the privileged CSRs exist in a supervisor and machine version
    that are used very similarly. Provide versions of the CSR names and
    fields that map to either the S-mode or M-mode variant depending on
    a new CONFIG_RISCV_M_MODE kconfig symbol.

    Contains contributions from Damien Le Moal
    and Paul Walmsley .

    Signed-off-by: Christoph Hellwig
    Acked-by: Thomas Gleixner # for drivers/clocksource, drivers/irqchip
    [paul.walmsley@sifive.com: updated to apply]
    Signed-off-by: Paul Walmsley

    Christoph Hellwig
     

05 Sep, 2019

1 commit

  • 2f12dbf19   riscv: don't use the rdtime(h) pseudo-instructions ... Browse Code »

    If we just use the CSRs that these map to directly the code is simpler
    and doesn't require extra inline assembly code. Also fix up the top-level
    comment in timer-riscv.c to not talk about the cycle count or mention
    details of the clocksource interface, of which this file is just a
    consumer.

    Signed-off-by: Christoph Hellwig
    Reviewed-by: Atish Patra
    Signed-off-by: Paul Walmsley

    Christoph Hellwig
     

07 Aug, 2019

1 commit

23 Mar, 2019

1 commit

  • 32d0be018   clocksource/drivers/riscv: Fix clocksource mask ... Browse Code »

    For all riscv architectures (RV32, RV64 and RV128), the clocksource
    is a 64 bit incrementing counter.

    Fix the clock source mask accordingly.

    Tested on both 64bit and 32 bit virt machine in QEMU.

    Fixes: 62b019436814 ("clocksource: new RISC-V SBI timer driver")
    Signed-off-by: Atish Patra
    Signed-off-by: Thomas Gleixner
    Reviewed-by: Anup Patel
    Cc: Albert Ou
    Cc: Daniel Lezcano
    Cc: linux-riscv@lists.infradead.org
    Cc: Palmer Dabbelt
    Cc: Anup Patel
    Cc: Damien Le Moal
    Cc: stable@vger.kernel.org
    Link: https://lkml.kernel.org/r/20190322215411.19362-1-atish.patra@wdc.com

    Atish Patra
     

23 Feb, 2019

1 commit

  • 26478b2f6   clocksource/drivers/riscv: Add required checks during clock source init ... Browse Code »

    Currently, clocksource registration happens for an invalid cpu for
    non-smp kernels. This lead to kernel panic as cpu hotplug registration
    will fail for those cpus. Moreover, riscv_hartid_to_cpuid can return
    errors now.

    Do not proceed if hartid or cpuid is invalid. Take this opportunity to
    print appropriate error strings for different failure cases.

    Signed-off-by: Atish Patra
    Reviewed-by: Anup Patel
    Reviewed-by: Palmer Dabbelt
    Signed-off-by: Daniel Lezcano

    Atish Patra
     

19 Dec, 2018

1 commit