10 Oct, 2020
1 commit
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Older ATF does not provide SMC call for SATA phy power on functionality and
therefore initialization of ahci_mvebu is failing when older version of ATF
is using. In this case phy_power_on() function returns -EOPNOTSUPP.This patch adds a new hflag AHCI_HFLAG_IGN_NOTSUPP_POWER_ON which cause
that ahci_platform_enable_phys() would ignore -EOPNOTSUPP errors from
phy_power_on() call.It fixes initialization of ahci_mvebu on Espressobin boards where is older
Marvell's Arm Trusted Firmware without SMC call for SATA phy power.This is regression introduced in commit 8e18c8e58da64 ("arm64: dts: marvell:
armada-3720-espressobin: declare SATA PHY property") where SATA phy was
defined and therefore ahci_platform_enable_phys() on Espressobin started
failing.Fixes: 8e18c8e58da64 ("arm64: dts: marvell: armada-3720-espressobin: declare SATA PHY property")
Signed-off-by: Pali Rohár
Tested-by: Tomasz Maciej Nowak
Cc: # 5.1+: ea17a0f153af: phy: marvell: comphy: Convert internal SMCC firmware return codes to errno
Signed-off-by: Jens Axboe
08 Apr, 2020
1 commit
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Add a new sysfs attribute to show how many NVMe devices are remapped.
Userspace like distro installer can use this info to ask user to change
the BIOS setting.Signed-off-by: Kai-Heng Feng
Signed-off-by: Jens Axboe
31 Aug, 2019
1 commit
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The Linux ahci driver has historically implemented a configuration fixup
for platforms / platform-firmware that fails to enable the ports prior
to OS hand-off at boot. The fixup was originally implemented way back
before ahci moved from drivers/scsi/ to drivers/ata/, and was updated in
2007 via commit 49f290903935 "ahci: update PCS programming". The quirk
sets a port-enable bitmap in the PCS register at offset 0x92.This quirk could be applied generically up until the arrival of the
Denverton (DNV) platform. The DNV AHCI controller architecture supports
more than 6 ports and along with that the PCS register location and
format were updated to allow for more possible ports in the bitmap. DNV
AHCI expands the register to 32-bits and moves it to offset 0x94.As it stands there are no known problem reports with existing Linux
trying to set bits at offset 0x92 which indicates that the quirk is not
applicable. Likely it is not applicable on a wider range of platforms,
but it is difficult to discern which platforms if any still depend on
the quirk.Rather than try to fix the PCS quirk to consider the DNV register layout
instead require explicit opt-in. The assumption is that the OS driver
need not touch this register, and platforms can be added with a new
boad_ahci_pcs7 board-id when / if problematic platforms are found in the
future. The logic in ahci_intel_pcs_quirk() looks for all Intel AHCI
instances with "legacy" board-ids and otherwise skips the quirk if the
board was matched by class-code.Reported-by: Stephen Douthit
Cc: Christoph Hellwig
Reviewed-by: Stephen Douthit
Signed-off-by: Dan Williams
Signed-off-by: Jens Axboe
21 May, 2019
1 commit
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Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license as published by
the free software foundation either version 2 or at your option any
later version this program is distributed in the hope that it will
be useful but without any warranty without even the implied warranty
of merchantability or fitness for a particular purpose see the gnu
general public license for more details you should have received a
copy of the gnu general public license along with this program see
the file copying if not write to the free software foundation 675
mass ave cambridge ma 02139 usaextracted by the scancode license scanner the SPDX license identifier
GPL-2.0-or-later
has been chosen to replace the boilerplate/reference in 52 file(s).
Signed-off-by: Thomas Gleixner
Reviewed-by: Jilayne Lovejoy
Reviewed-by: Steve Winslow
Reviewed-by: Kate Stewart
Reviewed-by: Allison Randal
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190519154042.342335923@linutronix.de
Signed-off-by: Greg Kroah-Hartman
12 Jan, 2019
1 commit
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Current implementation of the libahci does not take into account the
new PHY framework. Correct the situation by adding a call to
phy_set_mode() before phy_power_on().PHYs should also be handled at suspend/resume time. For this, call
ahci_platform_enable/disable_phys() at suspend/resume_host() time. These
calls are guarded by a HFLAG (AHCI_HFLAG_SUSPEND_PHYS) that the user of
the libahci driver must set manually in hpriv->flags at probe time. This
is to avoid breaking users that have not been tested with this change.Reviewed-by: Hans de Goede
Suggested-by: Grzegorz Jaszczyk
Signed-off-by: Miquel Raynal
Signed-off-by: Jens Axboe
03 Sep, 2018
2 commits
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The SoC R40 AHCI controller need a PHY regulator to work.
But since the PHY is embedded in the controller, we cannot do a DT node for it,
since phy-supply works only in node with a PHY compatible.
So this patch adds a way to add an optional phy-supply regulator on AHCI controller node.Acked-by: Maxime Ripard
Reviewed-by: Hans de Goede
Signed-off-by: Corentin Labbe
Signed-off-by: Jens Axboe -
The SoC R40 AHCI controller need a regulator to work.
So this patch add a way to add an optional regulator on AHCI controller.Acked-by: Maxime Ripard
Reviewed-by: Hans de Goede
Signed-off-by: Corentin Labbe
Signed-off-by: Jens Axboe
22 Aug, 2018
1 commit
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Add support to get and control a list of resets for the device
as optional and shared. These resets must be kept de-asserted until
the device is enabled.This is specified as shared because some SoCs like UniPhier series
have common reset controls with all ahci controller instances.However, according to Thierry's view,
https://www.spinics.net/lists/linux-ide/msg55357.html
some hardware-specific drivers already use their own resets,
and the common reset make a path to occur double controls of resets.The ahci_platform_get_resources() can get and control the reset
only when the second argument includes AHCI_PLATFORM_GET_RESETS bit.Suggested-by: Hans de Goede
Cc: Thierry Reding
Signed-off-by: Kunihiko Hayashi
Reviewed-by: Hans de Goede
Signed-off-by: Tejun Heo
06 Jun, 2018
1 commit
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Pull libata updates from Tejun Heo:
- libata has always been limiting the maximum queue depth to 31, with
one entry set aside mostly for historical reasons. This didn't use to
make much difference but Jens found out that modern hard drives can
actually perform measurably better with the extra one queue depth.
Jens updated libata core so that it can make use of full 32 queue
depth- Damien updated command retry logic in error handling so that it
doesn't unnecessarily retry when upper layer (SCSI) is gonna handle
them- A couple misc changes
* 'for-4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata:
sata_fsl: use the right type for tag bitshift
ahci: enable full queue depth of 32
libata: don't clamp queue depth to ATA_MAX_QUEUE - 1
libata: add extra internal command
sata_nv: set host can_queue count appropriately
libata: remove assumption that ATA_MAX_QUEUE - 1 is the max
libata: use ata_tag_internal() consistently
libata: bump ->qc_active to a 64-bit type
libata: convert core and drivers to ->hw_tag usage
libata: introduce notion of separate hardware tags
libata: Fix command retry decision
libata: Honor RQF_QUIET flag
libata: Make ata_dev_set_mode() less verbose
libata: Fix ata_err_string()
libata: Fix comment typo in ata_eh_analyze_tf()
sata_nv: don't use block layer bounce buffer
ata: hpt37x: Convert to use match_string() helper
12 May, 2018
1 commit
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This changes the AHCI queue depth from 31 to 32, as libata now
fully supports it. Now regular IO requests can utilize the full
tag space of SATA, not just 31. For IOPS constrained workloads,
this can result in a ~3% bump in performance.Signed-off-by: Jens Axboe
Signed-off-by: Tejun Heo
27 Apr, 2018
1 commit
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Marvell armada37xx, armada7k and armada8k share the same
AHCI sata controller IP, and currently there is an issue
(Errata Ref#226)that the SATA can not be detected via SATA
Port-MultiPlayer(PMP). After debugging, the reason is
found that the value of Port-x FIS-based Switching Control
(PxFBS@0x40) became wrong.
According to design, the bits[11:8, 0] of register PxFBS
are cleared when Port Command and Status (0x18) bit[0]
changes its value from 1 to 0, i.e. falling edge of Port
Command and Status bit[0] sends PULSE that resets PxFBS
bits[11:8; 0].
So it needs save the port PxFBS register before PxCMD
ST write and restore the port PxFBS register afterwards
in ahci_stop_engine().This commit allows drivers to override ahci_stop_engine
behavior for use by the Marvell AHCI driver(and potentially
other drivers in the future).Signed-off-by: Evan Wang
Cc: Ofer Heifetz
Cc: Tejun Heo
Cc: Thomas Petazzoni
Signed-off-by: Tejun Heo
10 Apr, 2018
1 commit
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This reverts commit f0f56716fc3e5d547fd7811eb218a30ed0695605.
According to Thierry's view,
https://www.spinics.net/lists/linux-ide/msg55357.html
some hardware-specific drivers already use their own resets,
and the common reset might make a path to occur double controls of resets.For now, revert the commit that adds reset control support to ahci-platform,
and hold until the solution is confirmed not be affect all hardware-specific
drivers.Fixes: f0f56716fc3e ("ata: ahci-platform: add reset control support")
Reported-by: Thierry Reding
Suggested-by: Hans de Goede
Acked-by: Hans de Goede
Signed-off-by: Kunihiko Hayashi
Signed-off-by: Tejun Heo
26 Mar, 2018
1 commit
-
Add support to get and control a list of resets for the device
as optional and shared. These resets must be kept de-asserted until
the device is enabled.This is specified as shared because some SoCs like UniPhier series
have common reset controls with all ahci controller instances.Signed-off-by: Kunihiko Hayashi
Reviewed-by: Hans de Goede
Signed-off-by: Tejun Heo
12 Dec, 2017
1 commit
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On many laptops setting a different LPM policy then unknown /
max_performance can lead to power-savings of 1.0 - 1.5 Watts (when idle).Modern ultrabooks idle around 6W (at 50% screen brightness), 1.0 - 1.5W
is a significant chunk of this.There are some performance / latency costs to enabling LPM by default,
so it is desirable to make it possible to set a different LPM policy
for mobile / laptop variants of chipsets / "South Bridges" vs their
desktop / server counterparts. Also enabling LPM by default is not
entirely without risk of regressions. At least min_power is known to
cause issues with some disks, including some reports of data corruption.This commits adds a new ahci.mobile_lpm_policy kernel cmdline option,
which defaults to a new SATA_MOBILE_LPM_POLICY Kconfig option so that
Linux distributions can choose to set a LPM policy for mobile chipsets
by default.The reason to have both a kernel cmdline option and a Kconfig default
value for it, is to allow easy overriding of the default to allow
trouble-shooting without needing to rebuild the kernel.Signed-off-by: Hans de Goede
Signed-off-by: Tejun Heo
20 Oct, 2017
1 commit
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In preparation for unconditionally passing the struct timer_list pointer to
all timer callbacks, switch to using the new timer_setup() and from_timer()
to pass the timer pointer explicitly. Adds a pointer back to link
structure.Signed-off-by: Kees Cook
Signed-off-by: Thomas Gleixner
Acked-by: Tejun Heo
Cc: linux-ide@vger.kernel.org
Link: https://lkml.kernel.org/r/20171016215658.GA101965@beast
23 Jun, 2017
2 commits
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While most hardware will simply ignore a write to a read-only register,
some hardware will signal an abort if this occurs.This commit introduces the flag AHCI_HFLAG_NO_WRITE_TO_RO to prevent the
AHCI library from attempting to write to the HOST_CAP, HOST_CAP2, and
HOST_PORTS_IMPL registers which may be read-only.Signed-off-by: Doug Berger
Signed-off-by: Tejun Heo -
Some hardware is capable of supporting Aggresive Link Power Management
even though it is not indicated by the Host Capability register.This commit adds the AHCI_HFLAG_YES_ALPM flag to the AHCI library to
allow indication of this quirk when the Host Capability register is
Read Only and therefore cannot be changed.Signed-off-by: Doug Berger
Signed-off-by: Tejun Heo
16 May, 2017
1 commit
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The libata documentation is now using ReST. Update references
to it to point to the new place.Signed-off-by: Mauro Carvalho Chehab
Acked-by: Bartlomiej Zolnierkiewicz
Signed-off-by: Tejun Heo
31 Jan, 2017
1 commit
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We need a way to retrieve the information about the online state of
the link in the ahci-da850 driver.Create a new function: ahci_do_hardreset() which is called from
ahci_hardreset() for backwards compatibility, but has an additional
argument: 'online' - which can be used to check if the link is online
after this function returns.The new routine will be used in the ahci-da850 driver to avoid code
duplication when implementing a workaround for tha da850 SATA
controller quirk/instability.Signed-off-by: Bartosz Golaszewski
Acked-by: Tejun Heo
Signed-off-by: Sekhar Nori
07 Sep, 2016
1 commit
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Use the new pci_alloc_irq_vectors API to allocate MSI-X and MSI vectors.
The big advantage over the old code is that we can use the same API for
MSI and MSI-X, and that we don't need to store the MSI-X vector mapping
in driver-private data structures.This first conversion keeps the probe order as-is: MSI-X multi vector,
MSI multi vector, MSI single vector, MSI-X single vector and last a
single least legacy interrupt line. There is one small change of
behavior: we now check the "MSI Revert to Single Message" flag for
MSI-X in addition to MSI.Because the API to find the Linux IRQ number for a MSI/MSI-X vector
is PCI specific, but libahaci is bus-agnostic I had to a
get_irq_vector function pointer to struct ahci_host_priv. The
alternative would be to move the multi-vector case of ahci_host_activate
to ahci.c and just call ata_host_activate directly from the others
users of ahci_host_activate.Signed-off-by: Christoph Hellwig
Signed-off-by: Tejun Heo
19 Feb, 2016
1 commit
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This allows sysfs nodes to read the cached value directly instead of
powering up possibly runtime suspended controller.Signed-off-by: Mika Westerberg
Signed-off-by: Tejun Heo
11 Feb, 2016
2 commits
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The flexibility to override the irq handles in the LLD's are already
present, so controllers implementing a edge trigger latch can
implement their own interrupt handler inside the driver. This patch
removes the AHCI_HFLAG_EDGE_IRQ support from libahci and moves edge
irq handling to ahci_xgene.tj: Minor update to description.
Signed-off-by: Suman Tripathi
Signed-off-by: Tejun Heo -
This patch implements the capability to override the generic AHCI
interrupt handler so that specific ahci drivers can implement their
own custom interrupt handler routines. It also exports
ahci_handle_port_intr so that custom irq_handler implementations can
use it.tj: s/ahci_irq_handler/irq_handler/ and updated description.
Signed-off-by: Suman Tripathi
Signed-off-by: Tejun Heo
26 Jan, 2016
1 commit
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The AHCI driver code stops and starts port DMA engines at will
without considering the power state of the particular port. The
AHCI specification isn't very clear on how to handle this scenario,
leaving implementation open to interpretation.Broadcom's STB SATA host controller is unable to handle port DMA
controller restarts when the port in question is in low power mode.
When a port enters partial or slumber mode, its PHY is powered down.
When a controller restart is requested, the controller's internal
state machine expects the PHY to be brought back up by software which
never happens in this case, resulting in failures.To avoid this situation, logic is added to manually wake up the port
just before its DMA engine is stopped, if the port happens to be in
a low power state. HBA initiated power management ensures that the port
eventually returns to its configured low power state, when the link is
idle (as per the conditions listed in the spec). A new host flag is also
added to ensure this logic is only exercised for hosts with the above
limitation.tj: Formatting changes.
Signed-off-by: Danesh Petigara
Reviewed-by: Markus Mayer
Signed-off-by: Tejun Heo
07 Dec, 2015
1 commit
-
Quoting Arnd:
The AHCI driver is used for some on-chip devices that do not use PCI
for probing, and it can be built even when CONFIG_PCI is disabled, but
that now results in a build failure:ata/libahci.c: In function 'ahci_host_activate_multi_irqs':
ata/libahci.c:2475:4: error: invalid use of undefined type 'struct msix_entry'
ata/libahci.c:2475:21: error: dereferencing pointer to incomplete type 'struct msix_entry'Add ifdef CONFIG_PCI_MSI infrastructure to compile out the multi-msi and
multi-msix code.Reported-by: Arnd Bergmann
Tested--by: Arnd Bergmann
[arnd: fix up pci enabled case]
Reported-by: Paul Gortmaker
Fixes: d684a90d38e2 ("ahci: per-port msix support")
Signed-off-by: Dan Williams
Signed-off-by: Tejun Heo
17 Nov, 2015
2 commits
-
This field in achi_port_priv was only used to support threaded
interrupts. Now that we are hardirq only it can be deleted.Signed-off-by: Dan Williams
Signed-off-by: Tejun Heo -
Some AHCI controllers support per-port MSI-X vectors. At the same time
the Linux AHCI driver needs to support one-off architectures that
implement a single MSI-X vector for all ports. The heuristic for
enabling AHCI ports becomes, in order of preference:1/ per-port multi-MSI-X
2/ per-port multi-MSI
3/ single MSI
4/ single MSI-X
5/ legacy INTX
This all depends on AHCI implementations with potentially broken MSI-X
requesting less vectors than the number of ports. If this assumption is
violated we will need to start explicitly white-listing AHCI-MSIX
implementations.Reported-by: Ricardo Neri
[ricardo: fix struct msix_entry handling]
Reported-by: kernel test robot
Signed-off-by: Dan Williams
Signed-off-by: Tejun Heo
01 Oct, 2015
1 commit
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If the AHCI ports' HPCP or ESP bits are set, the port
should be considered external (e.g. eSATA) and is marked
as removable. Userspace tools like udisks then treat it
like an usb drive.With this patch applied, when I plug a drive into the esata port,
KDE pops up a window asking what to do with the drives(s), just
like it does for any random USB stick.Removability is indicated to the upper layers by way of the
SCSI RMB bit, as I haven't found another way to signal
userspace to treat a sata disk like any usb stick.Signed-off-by: Manuel Lauss
Signed-off-by: Tejun Heo
03 Jun, 2015
1 commit
-
Currently, ahci supports only msi and intx. To also support msix the
handling of the irq number need to be changed. The irq number for msix
devices is taken from msi_list instead of pci_dev. Thus, the irq
number of a device needs to be stored in struct ahci_host_priv now.
This allows the host controller to be activated in a generic way.This change is only intended for ahci drivers. For that reason the irq
number is stored in struct ahci_host_priv used only by ahci drivers.
Thus, the ABI changes only for ahci_host_activate(), but existing ata
drivers (about 50) are unaffected and keep unchanged. All users of
ahci_host_activate() have been updated.While touching drivers/ata/libahci.c, doing a small code cleanup in
ahci_port_start().Signed-off-by: Robert Richter
Signed-off-by: Tejun Heo
10 May, 2015
1 commit
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This patch adds the support to handle HOST_IRQ_STAT as edge trigger
latch.Signed-off-by: Suman Tripathi
Signed-off-by: Tejun Heo
29 Jan, 2015
1 commit
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The owner module reference of the ahci platform's scsi_host is
initialized to libahci_platform's one, because these drivers use a
scsi_host_template defined in libahci_platform. So these drivers can
be unloaded even if the scsi device is being accessed.This fixes it by pushing the scsi_host_template from libahci_platform
to all leaf drivers. The scsi_host_template is passed through a new
argument of ahci_platform_init_host().Signed-off-by: Akinobu Mita
Signed-off-by: Tejun Heo
Cc: Hans de Goede
Cc: Christoph Hellwig
Cc: "James E.J. Bottomley"
Cc: linux-ide@vger.kernel.org
Cc: linux-scsi@vger.kernel.org
19 Jan, 2015
1 commit
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The current implementation of the libahci allows using multiple PHYs
but not multiple regulators. This patch adds the support of multiple
regulators. Until now it was mandatory to have a PHY under a subnode,
now a port subnode can contain either a regulator or a PHY (or both).In order to be able to asociate a port with a regulator the port are
now a platform device in the device tree case.There was only one driver which used directly the regulator field of
the ahci_host_priv structure. To preserve the bisectability the change
in the ahci_imx driver was done in the same patch.Signed-off-by: Gregory CLEMENT
Acked-by: Hans de Goede
Signed-off-by: Tejun Heo
06 Oct, 2014
3 commits
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As described in AHCI v1.0 specification chapter 10.6.2.2
"Multiple MSI Based Messages" generation of interrupts
is not controlled through the HOST_IRQ_STAT register.Considering MMIO access is expensive remove unnecessary
reading and writing of HOST_IRQ_STAT register.Further, serializing access to the host data is no longer
needed and the interrupt service routine can avoid competing
on the host lock.Signed-off-by: Alexander Gordeev
Suggested-by: "Jiang, Dave"
Signed-off-by: Tejun Heo
Cc: "Jiang, Dave"
Cc: linux-ide@vger.kernel.org -
Currently host activation done by calling either function
ahci_host_activate() or ata_host_activate(). Consolidate
the code by only calling ahci_host_activate() for all AHCI
devices.Signed-off-by: Alexander Gordeev
Signed-off-by: Tejun Heo
Cc: linux-ide@vger.kernel.org -
This update is a prerequisite for consolidation of
AHCI host activation code within ahci_host_activate()
function.Signed-off-by: Alexander Gordeev
Signed-off-by: Tejun Heo
Cc: linux-ide@vger.kernel.org
28 Sep, 2014
1 commit
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Sharing Last Message (SLM) mode is currently checked in two
functions: ahci_host_activate() and ahci_init_interrupts().
This update consolidates SLM mode check with activation of
multiple MSIs mode.Signed-off-by: Alexander Gordeev
Signed-off-by: Tejun Heo
Cc: linux-ide@vger.kernel.org
23 Sep, 2014
1 commit
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Qualcomm IPQ806x SoCs with SATA controllers need 5 clocks to be enabled.
Signed-off-by: Kumar Gala
Reviewed-by: Hans de Goede
Signed-off-by: Tejun Heo
31 Jul, 2014
3 commits
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The current implementation of the libahci does not allow to use multiple
PHYs. This patch adds the support of multiple PHYs by the libahci while
keeping the old bindings valid for device tree compatibility.This introduce a new way of defining SATA ports in the device tree, with
one port per sub-node. This as the advantage of allowing a per port
configuration. Because some ports may be accessible but disabled in the
device tree, the port_map mask is computed automatically when using
this.Signed-off-by: Antoine Ténart
Acked-by: Hans de Goede
Acked-by: Kishon Vijay Abraham I
Signed-off-by: Tejun Heo -
This patch moves force_port_map and mask_port_map into the
ahci_host_priv structure. This allows to modify them into the AHCI
framework. This is needed by the new dt bindings representing ports as
the port_map mask is computed automatically.Parameters modifying force_port_map, mask_port_map and flags have been
removed from the ahci_platform_init_host() function, and inputs in the
ahci_host_priv structure are now directly filed.Signed-off-by: Antoine Ténart
Signed-off-by: Tejun Heo -
…j/libata into for-3.17
The scheduled ahci platform patches depend on change in
for-3.16-fixes. Pull it into for-3.17.Signed-off-by: Tejun Heo <tj@kernel.org>
