08 Jan, 2021
1 commit
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Keep the EQOS clocks always on to wrokaround the system hang issue when
doing suspend/resume stress test. The root cause is still under debug.
For now, we just add this workaround to make sure the system suspend/resume
function is ok when EQOS is enanble. this workaround will be removed
when the root cause is found.(cherry-picked from kernel 5.4, and refined by Joakim.)
Reviewed-by: Fugang Duan
Reviewed-by: Li Jun
Signed-off-by: Jacky Bai
Signed-off-by: Joakim Zhang
07 Jan, 2021
1 commit
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Since CPU clocks are managed by CPUFREQ, do not enable
runtime PM otherwise rpm gets out of status as cpufreq
also manages clock states.Signed-off-by: Nitin Garg
Reviewed-by: Dong Aisheng
06 Jan, 2021
1 commit
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Add flag 'CLK_SET_RATE_PARENT' to 'IMX7D_LCDIF_PIXEL_ROOT_SRC' to
propagate rate changes from LCDIF pixel clock to video PLL which
can provide more accurate clock rate for LCDIF pixel clock.Signed-off-by: Fancy Fang
Reviewed-by: Robby Cai
04 Jan, 2021
1 commit
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This is the 5.10.4 stable release
* tag 'v5.10.4': (717 commits)
Linux 5.10.4
x86/CPU/AMD: Save AMD NodeId as cpu_die_id
drm/edid: fix objtool warning in drm_cvt_modes()
...Signed-off-by: Jason Liu
Conflicts:
drivers/gpu/drm/imx/dcss/dcss-plane.c
drivers/media/i2c/ov5640.c
30 Dec, 2020
16 commits
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commit 6160aca443148416994c022a35c77daeba948ea6 upstream.
Return values from read_dt_param() will be either TRUE (1) or
FALSE (0), while dfll_fetch_pwm_params() returns 0 on success
or an ERR code on failure.So this patch fixes the bug of returning 0 on failure.
Fixes: 36541f0499fe ("clk: tegra: dfll: support PWM regulator control")
Cc:
Signed-off-by: Nicolin Chen
Signed-off-by: Thierry Reding
Signed-off-by: Greg Kroah-Hartman -
commit 6f37689cf6b38fff96de52e7f0d3e78f22803ba0 upstream.
There is an error in the current code that the XTAL MODE
pin was set to NB MPP1_31 which should be NB MPP1_9.
The latch register of NB MPP1_9 has different offset of 0x8.Signed-off-by: Terry Zhou
[pali: Fix pin name in commit message]
Signed-off-by: Pali Rohár
Fixes: 7ea8250406a6 ("clk: mvebu: Add the xtal clock for Armada 3700 SoC")
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20201106100039.11385-1-pali@kernel.org
Reviewed-by: Marek Behún
Signed-off-by: Stephen Boyd
Signed-off-by: Greg Kroah-Hartman -
commit 11a163f2c7d6a9f27ce144cd7e367a81c851621a upstream.
The previous code assumed that a higher hardware value always resulted
in a bigger divider, which is correct for the regular clocks, but is
an invalid assumption when a divider table is provided for the clock.Perfect example of this is the PLL0_HALF clock, which applies a /2
divider with the hardware value 0, and a /1 divider otherwise.Fixes: a9fa2893fcc6 ("clk: ingenic: Add support for divider tables")
Cc: # 5.2
Signed-off-by: Paul Cercueil
Link: https://lore.kernel.org/r/20201212135733.38050-1-paul@crapouillou.net
Signed-off-by: Stephen Boyd
Signed-off-by: Greg Kroah-Hartman -
[ Upstream commit 4b003f5fcadfa2d0e087e907b0c65d023f6e29fb ]
Commit 45c940184b501fc6 ("dt-bindings: clk: versaclock5: convert to
yaml") accidentally changed "idt,voltage-microvolts" to
"idt,voltage-microvolt" in the DT bindings, while the driver still used
the former.Update the driver to match the bindings, as
Documentation/devicetree/bindings/property-units.txt actually recommends
using "microvolt".Fixes: 260249f929e81d3d ("clk: vc5: Enable addition output configurations of the Versaclock")
Signed-off-by: Geert Uytterhoeven
Link: https://lore.kernel.org/r/20201218125253.3815567-1-geert+renesas@glider.be
Reviewed-by: Luca Ceresoli
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
[ Upstream commit 48f68de00c1405351fa0e7bc44bca067c49cd0a3 ]
Two clock divider tables are missing sentinel at the end. Effect of that
is that clock framework reads past the last entry. Fix that with adding
sentinel at the end.Issue was discovered with KASan.
Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
Fixes: c6a0637460c2 ("clk: sunxi-ng: Add A64 clocks")
Signed-off-by: Jernej Skrabec
Link: https://lore.kernel.org/r/20201202203817.438713-1-jernej.skrabec@siol.net
Acked-by: Maxime Ripard
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
[ Upstream commit d2d94fc567624f96187e8b52083795620f93e69f ]
Some resource should be released in the error handling path of the probe
function, as already done in the remove function.The remove function was fixed in commit bf416bd45738 ("clk: s2mps11: Add
missing of_node_put and of_clk_del_provider")Fixes: 7cc560dea415 ("clk: s2mps11: Add support for s2mps11")
Signed-off-by: Christophe JAILLET
Link: https://lore.kernel.org/r/20201212122818.86195-1-christophe.jaillet@wanadoo.fr
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
[ Upstream commit 01324f9e88b5cfc1f4c26eef66bdcb52596c9af8 ]
The sam9x60 doesn't have the MOSCXTBY bit to enable the crystal oscillator
bypass.Fixes: 01e2113de9a5 ("clk: at91: add sam9x60 pmc driver")
Reported-by: Claudiu Beznea
Signed-off-by: Alexandre Belloni
Link: https://lore.kernel.org/r/20201202125816.168618-1-alexandre.belloni@bootlin.com
Reviewed-by: Claudiu Beznea
Tested-by: Claudiu Beznea
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
[ Upstream commit 91274497c79170aaadc491d4ffe4de35495a060d ]
pmc_data_allocate() has been changed. pmc_data_free() was removed.
Adapt the code taking this into consideration. With this the programmable
clocks were also saved in sama7g5_pmc so that they could be later
referenced.Fixes: cb783bbbcf54 ("clk: at91: sama7g5: add clock support for sama7g5")
Signed-off-by: Claudiu Beznea
Reviewed-by: Tudor Ambarus
Tested-by: Tudor Ambarus
Link: https://lore.kernel.org/r/1605800597-16720-2-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
[ Upstream commit be439cc4c404f646a8ba090fa786d53c10926b12 ]
Add MODULE_DEVICE_TABLE() so as to be able to use the driver as a
module. More precisely, for the driver to be loaded automatically at
boot.Fixes: 1bc95972715a ("clk: bcm: Add BCM2711 DVP driver")
Signed-off-by: Nicolas Saenz Julienne
Link: https://lore.kernel.org/r/20201202103518.21889-1-nsaenzjulienne@suse.de
Reviewed-by: Maxime Ripard
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
[ Upstream commit 8c6239f6e95f583bb763d0228e02d4dd0fb3d492 ]
If clk_register fails, we should goto free branch
before function returns to prevent memleak.Fixes: 163152cbbe321 ("clk: ti: Add support for FAPLL on dm816x")
Reported-by: Hulk Robot
Signed-off-by: Zhang Qilong
Link: https://lore.kernel.org/r/20201113131623.2098222-1-zhangqilong3@huawei.com
Acked-by: Tony Lindgren
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
[ Upstream commit 5bf5861d6ea6c3f4b38fc8fda2062b2dc44ac63d ]
The periph_clks[] array contains duplicated entry for Security Engine
clock which was meant to be defined for T210, but it wasn't added
properly. This patch corrects the T210 SE entry and fixes the following
error message on T114/T124: "Tegra clk 127: register failed with -17".Fixes: dc37fec48314 ("clk: tegra: periph: Add new periph clks and muxes for Tegra210")
Tested-by Nicolas Chauvet
Reported-by Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
Link: https://lore.kernel.org/r/20201025224212.7790-1-digetx@gmail.com
Acked-by: Thierry Reding
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
[ Upstream commit 6d37a8d192830267e6b10a6d57ae28d2e89097e7 ]
I would repeat the same commit message that was in commit 5e4b7e82d497
("clk: qcom: gcc-sdm845: Use floor ops for sdcc clks") but it seems
silly to do so when you could just go read that commit.NOTE: this is actually extra terrible because we're missing the 50 MHz
rate in the table (see the next patch AKA ("clk: qcom: gcc-sc7180: Add
50 MHz clock rate for SDC2")). That means then when you run an older
SD card it'll try to clock it at 100 MHz when it's only specced to run
at 50 MHz max. As you can probably guess that doesn't work super
well.Signed-off-by: Douglas Anderson
Fixes: 17269568f726 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180")
Link: https://lore.kernel.org/r/20201210102234.1.I096779f219625148900fc984dd0084ed1ba87c7f@changeid
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
[ Upstream commit 14653942de7f63e21ece32e3901f09a248598a43 ]
The R-Car V3U clock driver defines the R and OSC clocks using R-Car Gen3
clock types. However, The R-Car V3U clock driver does not use the R-Car
Gen3 clock driver core, hence registering the R and OSC clocks fails:renesas-cpg-mssr e6150000.clock-controller: Failed to register core clock osc: -22
renesas-cpg-mssr e6150000.clock-controller: Failed to register core clock r: -22Fix this by introducing clock definition macros specific to R-Car V3U.
Note that rcar_r8a779a0_cpg_clk_register() already handled the related
clock types. Drop the now unneeded include of rcar-gen3-cpg.h.Fixes: 17bcc8035d2d19fc ("clk: renesas: cpg-mssr: Add support for R-Car V3U")
Signed-off-by: Geert Uytterhoeven
Tested-by: Yoshihiro Shimoda
Reviewed-by: Yoshihiro Shimoda
Link: https://lore.kernel.org/r/20201109152614.2465483-1-geert+renesas@glider.be
Signed-off-by: Sasha Levin -
[ Upstream commit e81bed419f032824e7ddf8b5630153be6637e480 ]
If the device is removed we don't unregister the composite clock. Fix
that.Fixes: 9cd10205227c ("clk: fsl-sai: new driver")
Signed-off-by: Michael Walle
Link: https://lore.kernel.org/r/20201105192746.19564-2-michael@walle.cc
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
[ Upstream commit bae69bfa3a586493469078ec4ca35499b754ba5c ]
When building only G12A, ensure that VID_PLL_DIV clock driver is
selected, otherwise results in this build error:ERROR: modpost: "meson_vid_pll_div_ro_ops" [drivers/clk/meson/g12a.ko] undefined!
Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller")
Signed-off-by: Kevin Hilman
Signed-off-by: Jerome Brunet
Link: https://lore.kernel.org/r/20201118190930.34352-1-khilman@baylibre.com
Signed-off-by: Sasha Levin -
The sys2_pll_50m should be one of the clock sels of PCIE_AUX clock,
otherwise the sys2_pll_500m.Signed-off-by: Richard Zhu
29 Dec, 2020
1 commit
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Since the CG of the AXI clock would be handled by the composite clock
"IMX8MP_CLK_HSIO_AXI" instead, remove the axi cg clock introduced
by LF-2881-1.This reverts commit b73dd6ece1da174e0514587ff4501c2ce49aa790.
Signed-off-by: Richard Zhu
Reviewed-by: Jun Li
Reviewed-by: Ye Li
18 Dec, 2020
1 commit
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* origin/clock/s32: (9 commits)
LF-632 clk: s32v234: Fix "enetpll_dfs3" position in sdhc_sels
clk: s32v234: Enable FlexCAN clock
clk: s32v234: Add definitions for CAN clocks
clk: s32v234: Initial enet clk support
clk: s32v234: Add dfs clk
...
17 Dec, 2020
1 commit
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Add imx8qm hdmi rx subsystem lpcg clocks.
Signed-off-by: Sandor Yu
Reviewed-by: Robby Cai
14 Dec, 2020
17 commits
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According to the RM, MC_CGM_0_AC15_SC[SELCTL] needs to be 0b100 in order to
select ENET PLL DFS 4 as the source for SDHC_CLK. Omitting such a position
in the parents array will prevent clk_get_rate() (called from
sdhci-esdhc-imx.c) from determining the frequency of ipg_clk_perclk.Fixes: fba4afe47600 ("clk: s32v234: Initial enet clk support")
Signed-off-by: Stefan-Gabriel Mirea
Reviewed-by: Leonard Crestez -
Enable the clocks needed for FlexCAN support on Treerunner.
Signed-off-by: Chircu-Mare Bogdan-Petru
Signed-off-by: Stoica Cosmin-Stefan
Signed-off-by: Larisa Grigore
Signed-off-by: Stefan-Gabriel Mirea
Reviewed-by: Li Yang
Reviewed-by: Leonard Crestez -
Add ethernet clocks and dependencies (sys_pll, arm_pll)
Based on ALB v4.19.31_bsp23.0_rc2
Signed-off-by: Leonard Crestez
Reviewed-by: Fugang Duan -
Port from ALB v4.19.31_bsp23.0_rc2
Signed-off-by: Leonard Crestez
Reviewed-by: Fugang Duan -
Enable the clocks needed for uSDHC support on Treerunner.
Signed-off-by: Stoica Cosmin-Stefan
Signed-off-by: Larisa Grigore
Signed-off-by: Stefan-Gabriel Mirea -
Enable the clocks needed for LINFlexD UART support on Treerunner and make
use of them in the LINFlexD driver.Signed-off-by: Stoica Cosmin-Stefan
Signed-off-by: Adrian.Nitu
Signed-off-by: Larisa Grigore
Signed-off-by: Iustin Dumitrescu
Signed-off-by: Stefan-Gabriel Mirea
Signed-off-by: Leonard Crestez -
Add clock framework for Treerunner (S32V234), based on code from the i.MX
3.10.17 codebase[1]. Add clock definitions that are used in the clocks
vector (tree). At this point, the only PLL enabled is PERIPH-PLL.[1] https://source.codeaurora.org/external/imx/linux-imx/tree/?h=imx_3.10.17_1.0.0_ga_caf
Signed-off-by: Stoica Cosmin-Stefan
Signed-off-by: Larisa Grigore
Signed-off-by: Stefan-Gabriel Mirea -
For inamte linux, hws is not initialzied, so it will trigger panic
if not checking hws.Reviewed-by: Ye Li
Signed-off-by: Peng Fan -
Due to commit 82586f0aa1c2 (arm64: dts: imx8mp: correct
assigned-clock-rates for video_pll1), so remove unused
2079M clock from imx_pll1443x_tbl.Signed-off-by: Fancy Fang
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Add the IMX8MP_CLK_HSIO_AXI_CG clock mandatory required by iMX8MP PCIe.
Signed-off-by: Richard Zhu
Reviewed-by: Fugang Duan -
this support is similar as i.MX8MM.
for userspace monitor control of the K-divider dynamically,
we provide two interfaces to userspace: delta_k & pll_parameter1): delta_k is used to adjust the K divider in PLL based on small
steps;
2): the pll_parameter interface is used for get PLL's current
M-divider, P-divider, S-divider & K-divider setting in PLL registerexample for the usage of these two interfaces:
A): Get the current PLL setting of dividers:
root@imx8mmevk:~# cat /sys/kernel/debug/audio_pll_monitor/audio_pll1/pll_parameter
Mdiv: 0x106; Pdiv: 0x2; Sdiv: 0x3; Kdiv: 0x24ddB): if want to adjust the K-divider by a delta_k '1', then
echo 0x1 > /sys/kernel/debug/audio_pll_monitor/audio_pll1/delta_k;root@imx8mmevk:~# cat /sys/kernel/debug/audio_pll_monitor/audio_pll1/pll_parameter
Mdiv: 0x106; Pdiv: 0x2; Sdiv: 0x3; Kdiv: 0x24deC): if want to adjust the K-divider by a delta_k '-1', then
echo -1 > /sys/kernel/debug/audio_pll_monitor/audio_pll1/delta_k;root@imx8mmevk:~# cat /sys/kernel/debug/audio_pll_monitor/audio_pll1/pll_parameter
Mdiv: 0x106; Pdiv: 0x2; Sdiv: 0x3; Kdiv: 0x24dcSigned-off-by: Jacky Bai
Tested-by: Shengjiu Wang
Reviewed-by: Anson Huang -
For i.MX7D DRAM related mux clock, the clock source change is ONLY done
in busfreq low level asm code, and then calling clk API to sync the HW
clock status with clk tree, it never touches real clock source switch
via clk API, so CLK_SET_PARENT_GATE flag should NOT be added, otherwise,
DRAM's clock parent will be disabled when DRAM is active after audio
bus clock change, and system will hang.Signed-off-by: Anson Huang
Acked-by: Peng Fan
Reviewed-by: Jacky Bai -
The pm_runtime_get_sync needs to be called only when there is no bit
asserted yet but one is about to get asserted, while the pm_runtime_put
needs to be called only after the last asserted bit gets deasserted.
Also skip the entire thing if there is a driver that mistakenly calls
the deassert for its bit first, without ever asserting it.Signed-off-by: Abel Vesa
-
There is a chance the clocks might be gated while we're saving
the appropriate regs for runtime supend. There is no issue here by
using the imx_ccm_lock to also protect the reset bits. The alternative
would be to add a separate lock for the registers that hold reset bits.
That would complicate the logic since we would have to use different
locks for different registers.Signed-off-by: Abel Vesa
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cpufreq now supported parsing cpufreq default governor from bootargs,
for i.MX8QM which uses schedutil cpufreq governor, just need to add
"cpufreq.default_governor=SCHEDUTIL" in u-boot bootargs, then schedutil
cpufreq governor will be used for all CPUs, so remove the manual cpufreq
governor switch in kernel and will add the bootargs into u-boot by default.Signed-off-by: Anson Huang
Reviewed-by: Jacky Bai -
When testing dual Linux demo on imx8mp, it is found that there is no log
on the serial port belongs to the inmate Linux. The reason for the
problem is that the clock of uart4 is not turned on.Reviewed-by: Peng Fan
Signed-off-by: Alice Guo -
Remove all MLB clock setting for imx8qm/qxp.
Reviewed-by: Fugang Duan
Signed-off-by: Clark Wang
