01 Jul, 2022
1 commit
18 Dec, 2020
1 commit
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* origin/net/phy: (13 commits)
MLK-24295 net: phy: realtek: add dt property to enable clkout
MLK-24174-03 net: phy: tja11xx: add refclk source selection support
LF-1762-3 net: phy: replace '---help---' in Kconfig files with 'help'
LF-538 net: phy: tja11xx: add user interface to enable slave mode
drivers: net: phy: aquantia: enable USX AN for USXGMII protocol
...
14 Dec, 2020
13 commits
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Add dt property for user to enable clkout for MAC.
Reviewed-by: Richard Zhu
Signed-off-by: Fugang Duan -
Add below features support for both TJA1100 and TJA1101 cards:
- Add MII and RMII mode support.
- Add refclk in/out support for RMII.Reviewed-by: Richard Zhu
Signed-off-by: Fugang Duan -
Update Kconfig to cope with upstream change
commit 84af7a6194e4 ("checkpatch: kconfig: prefer 'help' over
'---help---'").Signed-off-by: Dong Aisheng
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Current phy driver only support master mode.
Add sysfs interface for user to danimiacally configure
the phy mode to master or slave.Reviewed-by: Richard Zhu
Signed-off-by: Fugang Duan -
Depending on FW defaults USX AN in AQR PHY must be explicitly enabled when
using USXGMII. Enable it based on interface type.Signed-off-by: Alex Marginean
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Do not set up protocols for speeds that are not supported by FW. Enabling
these protocols leads to link issues on system side.Signed-off-by: Alex Marginean
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Adds support for AQR112 and AQR412 which is mostly based on existing code
with the addition of code configuring the protocol on system side.
This allows changing the system side protocol without having to deploy a
different firmware on the PHY.Signed-off-by: Alex Marginean
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Add new property "at803x,vddio-1p8v" and "at803x,eee-disabled"
support.Signed-off-by: Fugang Duan
[ Aisheng: fix small merge conflict ]
[ Leo: Resolved conflicts rebasing to linux-next ]
Signed-off-by: Dong Aisheng -
The retimer doesn't get probed in linux due to the fact that it's a
non-standard clause-45 device. Hardcoding the phyid in device-tree
and adding custom routines for registry read/write operations
solves the issue.Signed-off-by: Florin Chiculita
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Software controller for IN112525_s03 retimer
Signed-off-by: Florin Chiculita
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* According to the AR8035 datasheet, smartEEE mode (active by default)
makes the PHY enters sleep after a configurable idle time. It does
this autonomously, without LPI (Low Power Idle) signals coming from MAC.
* Tested with ping (default of 1 second interval) over back-to-back
RGMII between 2 boards having AR8035 at both ends:
- Without patch:
225 packets transmitted, 145 received, 35% packet loss, time 229334ms
- With patch:
144 packets transmitted, 144 received, 0% packet loss, time 146378msSigned-off-by: Vladimir Oltean
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Signed-off-by: Camelia Groza
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In .mdio_bus_phy_may_suspend(), there check netdev is NULL to judge to set
phy to suspend status.netdev is NULL has three cases:
- phy is not found
- phy is found, match to general phy driver
- phy is found, match to specifical phy driverCase 1: phy is not found, cannot communicate by MDIO bus.
Case 2: phy is found:
if phy dev driver probe/bind err, netdev is not __open__ status,
mdio bus is unregistered.
if phy is detached, phy had entered suspended status.
Case 3: phy is found, phy is detached, phy had entered suspended status.So, in here, it shouldn't set phy to suspend by calling mdio bus.
In i.MX6UL evk/arm2 board, if down the ethx interface and do
suspend/resume, system will hang. Because after ethx down all clocks are
gated off, for general phy driver, unbind the phy device, for specifical
phy driver, no unbind the device, and the original driver call mdio bus to
set phy to suspend during system suspend, so system will hang since there
have mdio register access.
The patch can fix it.Signed-off-by: Fugang Duan
15 Nov, 2020
1 commit
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Add the missing clk_disable_unprepare() before return from
smsc_phy_probe() in the error handling case.Fixes: bedd8d78aba3 ("net: phy: smsc: LAN8710/20: add phy refclk in support")
Reported-by: Hulk Robot
Signed-off-by: Zhang Changzhong
Link: https://lore.kernel.org/r/1605180239-1792-1-git-send-email-zhangchangzhong@huawei.com
Signed-off-by: Jakub Kicinski
14 Nov, 2020
1 commit
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Selecting VSC8575 as a MACSec PHY was not correct
The relevant datasheet can be found here:
- VSC8575: https://www.microchip.com/wwwproducts/en/VSC8575History:
v1 -> v2:
- Corrected the sha in the "Fixes:" tagFixes: 1bbe0ecc2a1a ("net: phy: mscc: macsec initialization")
Signed-off-by: Steen Hegelund
Reviewed-by: Antoine Tenart
Link: https://lore.kernel.org/r/20201113091116.1102450-1-steen.hegelund@microchip.com
Signed-off-by: Jakub Kicinski
11 Nov, 2020
1 commit
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The RTL8401-internal PHY identifies as RTL8201CP, and the init
sequence in r8169, copied from vendor driver r8168, uses paged
operations. Therefore set the same paged operation callbacks as
for the other Realtek PHY's.Fixes: cdafdc29ef75 ("r8169: sync support for RTL8401 with vendor driver")
Signed-off-by: Heiner Kallweit
Link: https://lore.kernel.org/r/69882f7a-ca2f-e0c7-ae83-c9b6937282cd@gmail.com
Signed-off-by: Jakub Kicinski
03 Nov, 2020
1 commit
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gpiod_to_irq() never return 0, but returns negative in
case of error, check it and set gpio_irq to 0.Fixes: 73970055450e ("sfp: add SFP module support")
Signed-off-by: YueHaibing
Reviewed-by: Andrew Lunn
Link: https://lore.kernel.org/r/20201031031053.25264-1-yuehaibing@huawei.com
Signed-off-by: Jakub Kicinski
06 Oct, 2020
1 commit
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Rejecting non-native endian BTF overlapped with the addition
of support for it.The rest were more simple overlapping changes, except the
renesas ravb binding update, which had to follow a file
move as well as a YAML conversion.Signed-off-by: David S. Miller
05 Oct, 2020
1 commit
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Convert m88e1318_get_wol() to use the well implemented phy_read_paged()
instead of open coding it.Signed-off-by: Jisheng Zhang
Reviewed-by: Marek Behún
Reviewed-by: Andrew Lunn
Signed-off-by: David S. Miller
04 Oct, 2020
1 commit
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Currently the comparisons of u16 integers value and sopass_val with
less than zero for error checking is always false because the values
are unsigned. Fix this by making these variables int. This does not
affect the shift and mask operations performed on these variablesAddresses-Coverity: ("Unsigned compared against zero")
Fixes: 49fc23018ec6 ("net: phy: dp83869: support Wake on LAN")
Signed-off-by: Colin Ian King
Acked-by: Dan Murphy
Signed-off-by: David S. Miller
02 Oct, 2020
1 commit
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Realtek single-chip Ethernet PHY solutions can be separated as below:
10M/100Mbps: RTL8201X
1Gbps: RTL8211X
2.5Gbps: RTL8226/RTL8221X
RTL8226 is the first version for realtek that compatible 2.5Gbps single PHY.
Since RTL8226 is single port only, realtek changes its name to RTL8221B from
the second version.
PHY ID for RTL8226 is 0x001cc800 and RTL8226B/RTL8221B is 0x001cc840.RTL8125 is not a single PHY solution, it integrates PHY/MAC/PCIE bus
controller and embedded memory.Signed-off-by: Willy Liu
Signed-off-by: David S. Miller
30 Sep, 2020
2 commits
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in_interrupt() is ill defined and does not provide what the name
suggests. The usage especially in driver code is deprecated and a tree wide
effort to clean up and consolidate the (ab)usage of in_interrupt() and
related checks is happening.In this case the check covers only parts of the contexts in which these
functions cannot be called. It fails to detect preemption or interrupt
disabled invocations.As the functions which contain these warnings invoke mutex_lock() which
contains a broad variety of checks (always enabled or debug option
dependent) and therefore covers all invalid conditions already, there is no
point in having inconsistent warnings in those drivers. The conditional
return is not really valuable in practice either.Just remove them.
Signed-off-by: Sebastian Andrzej Siewior
Signed-off-by: Thomas Gleixner
Reviewed-by: Andrew Lunn
Signed-off-by: David S. Miller -
There are two chip pins named TXDLY and RXDLY which actually adds the 2ns
delays to TXC and RXC for TXD/RXD latching. These two pins can config via
4.7k-ohm resistor to 3.3V hw setting, but also config via software setting
(extension page 0xa4 register 0x1c bit13 12 and 11).The configuration register definitions from table 13 official PHY datasheet:
PHYAD[2:0] = PHY Address
AN[1:0] = Auto-Negotiation
Mode = Interface Mode Select
RX Delay = RX Delay
TX Delay = TX Delay
SELRGV = RGMII/GMII SelectionThis table describes how to config these hw pins via external pull-high or pull-
low resistor.It is a misunderstanding that mapping it as register bits below:
8:6 = PHY Address
5:4 = Auto-Negotiation
3 = Interface Mode Select
2 = RX Delay
1 = TX Delay
0 = SELRGV
So I removed these descriptions above and add related settings as below:
14 = reserved
13 = force Tx RX Delay controlled by bit12 bit11
12 = Tx Delay
11 = Rx Delay
10:0 = Test && debug settings reserved by realtekTest && debug settings are not recommend to modify by default.
Fixes: f81dadbcf7fd ("net: phy: realtek: Add rtl8211e rx/tx delays config")
Signed-off-by: Willy Liu
Signed-off-by: David S. Miller
29 Sep, 2020
3 commits
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Use kobj_to_dev() instead of container_of().
Signed-off-by: Wang Qing
Signed-off-by: David S. Miller -
Set the speed optimization bit on the DP83869 PHY.
Speed optimization, also known as link downshift, enables fallback to 100M
operation after multiple consecutive failed attempts at Gigabit link
establishment. Such a case could occur if cabling with only four wires
(two twisted pairs) were connected instead of the standard cabling with
eight wires (four twisted pairs).The number of failed link attempts before falling back to 100M operation is
configurable. By default, four failed link attempts are required before
falling back to 100M.Signed-off-by: Dan Murphy
Reviewed-by: Andrew Lunn
Signed-off-by: David S. Miller -
This adds WoL support on TI DP83869 for magic, magic secure, unicast and
broadcast.Signed-off-by: Dan Murphy
Reviewed-by: Andrew Lunn
Signed-off-by: David S. Miller
28 Sep, 2020
1 commit
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Fix build error by selecting MDIO_DEVRES for MDIO_THUNDER.
Fixes this build error:ld: drivers/net/phy/mdio-thunder.o: in function `thunder_mdiobus_pci_probe':
drivers/net/phy/mdio-thunder.c:78: undefined reference to `devm_mdiobus_alloc_size'Fixes: 379d7ac7ca31 ("phy: mdio-thunder: Add driver for Cavium Thunder SoC MDIO buses.")
Reported-by: kernel test robot
Signed-off-by: Randy Dunlap
Cc: Bartosz Golaszewski
Cc: Andrew Lunn
Cc: Heiner Kallweit
Cc: netdev@vger.kernel.org
Cc: David Daney
Reviewed-by: Andrew Lunn
Signed-off-by: David S. Miller
24 Sep, 2020
1 commit
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Add kerneldoc for the core PHY data structures, a few inline functions
and exported functions which are not already documented.v2
Typos
g/phy/PHY/sSigned-off-by: Andrew Lunn
Signed-off-by: David S. Miller
23 Sep, 2020
1 commit
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Two minor conflicts:
1) net/ipv4/route.c, adding a new local variable while
moving another local variable and removing it's
initial assignment.2) drivers/net/dsa/microchip/ksz9477.c, overlapping changes.
One pretty prints the port mode differently, whilst another
changes the driver to try and obtain the port mode from
the port node rather than the switch node.Signed-off-by: David S. Miller
22 Sep, 2020
2 commits
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BCM72113 features a 28nm integrated EPHY, add an entry to the driver for
it.Signed-off-by: Florian Fainelli
Reviewed-by: Andrew Lunn
Signed-off-by: David S. Miller -
Enable ALDPS(Advanced Link Down Power Saving) to save power when
link down.Signed-off-by: Jisheng Zhang
Reviewed-by: Andrew Lunn
Signed-off-by: David S. Miller
20 Sep, 2020
3 commits
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Update the fiber advertisement for speed and duplex modes with the
100base-FX full and half linkmode entries.Signed-off-by: Dan Murphy
Reviewed-by: Andrew Lunn
Reviewed-by: Florian Fainelli
Signed-off-by: David S. Miller -
Add the ability to advertise the Fiber connection if the strap or the
op-mode is configured for 100Base-FX.Auto negotiation is not supported on this PHY when in fiber mode.
Signed-off-by: Dan Murphy
Reviewed-by: Andrew Lunn
Reviewed-by: Florian Fainelli
Signed-off-by: David S. Miller -
Add entries for the 100base-FX full and half duplex supported modes.
$ ethtool eth0
Supported ports: [ FIBRE ]
Supported link modes: 100baseFX/Half 100baseFX/Full
Supported pause frame use: Symmetric Receive-only
Supports auto-negotiation: No
Supported FEC modes: Not reported
Advertised link modes: 100baseFX/Half 100baseFX/Full
Advertised pause frame use: No
Advertised auto-negotiation: No
Advertised FEC modes: Not reported
Speed: 100Mb/s
Duplex: Full
Auto-negotiation: off
Port: MII
PHYAD: 1
Transceiver: external
Supports Wake-on: gs
Wake-on: d
SecureOn password: 00:00:00:00:00:00
Current message level: 0x00000000 (0)Link detected: yes
Signed-off-by: Dan Murphy
Reviewed-by: Andrew Lunn
Reviewed-by: Florian Fainelli
Signed-off-by: David S. Miller
19 Sep, 2020
1 commit
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The internal Gigabit PHY on Broadcom STB chips has a digital clock which
drives its MDIO interface among other things, the driver now requests
and manage that clock during .probe() and .remove() accordingly.Because the PHY driver can be probed with the clocks turned off we need
to apply the dummy BMSR workaround during the driver probe function to
ensure subsequent MDIO read or write towards the PHY will succeed.Signed-off-by: Florian Fainelli
Reviewed-by: Andrew Lunn
Signed-off-by: David S. Miller
18 Sep, 2020
2 commits
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When phy_is_started() was added to catch incorrect PHY states,
phy_stop() would not be qualified against PHY_DOWN. It is possible to
reach that state when the PHY driver has been unbound and the network
device is then brought down.Fixes: 2b3e88ea6528 ("net: phy: improve phy state checking")
Signed-off-by: Florian Fainelli
Reviewed-by: Andrew Lunn
Signed-off-by: David S. Miller -
If we have unbound the PHY driver prior to calling phy_detach() (often
via phy_disconnect()) then we can cause a NULL pointer de-reference
accessing the driver owner member. The steps to reproduce are:echo unimac-mdio-0:01 > /sys/class/net/eth0/phydev/driver/unbind
ip link set eth0 downFixes: cafe8df8b9bc ("net: phy: Fix lack of reference count on PHY driver")
Signed-off-by: Florian Fainelli
Reviewed-by: Andrew Lunn
Signed-off-by: David S. Miller
12 Sep, 2020
1 commit
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LAN8814 is a low-power, quad-port triple-speed (10BASE-T/100BASETX/1000BASE-T)
Ethernet physical layer transceiver (PHY). It supports transmission and
reception of data on standard CAT-5, as well as CAT-5e and CAT-6, unshielded
twisted pair (UTP) cables.LAN8814 supports industry-standard QSGMII (Quad Serial Gigabit Media
Independent Interface) and Q-USGMII (Quad Universal Serial Gigabit Media
Independent Interface) providing chip-to-chip connection to four Gigabit
Ethernet MACs using a single serialized link (differential pair) in each
direction.The LAN8814 SKU supports high-accuracy timestamping functions to
support IEEE-1588 solutions using Microchip Ethernet switches, as well as
customer solutions based on SoCs and FPGAs.The LAN8804 SKU has same features as that of LAN8814 SKU except that it does
not support 1588, SyncE, or Q-USGMII with PCH/MCH.This adds support for 10BASE-T, 100BASE-TX, and 1000BASE-T,
QSGMII link with the MAC.Signed-off-by: Divya Koppera
Signed-off-by: David S. Miller
