Eric Lee / smarc-fsl-linux-kernel

14 Oct, 2010

1 commit

  • 4267ea72b   oprofile/fsl emb: Don't set MSR[PMM] until after clearing the interrupt. ... Browse Code »

    On an arch 2.06 hypervisor, a pending perfmon interrupt will be delivered
    to the hypervisor at any point the guest is running, regardless of
    MSR[EE]. In order to reflect this interrupt, the hypervisor has to mask
    the interrupt in PMGC0 -- and set MSRP[PMMP] to intercept futher guest
    accesses to the PMRs to detect when to unmask (and prevent the guest from
    unmasking early, or seeing inconsistent state).

    This has the side effect of ignoring any changes the guest makes to
    MSR[PMM], so wait until after the interrupt is clear, and thus the
    hypervisor should have cleared MSRP[PMMP], before setting MSR[PMM]. The
    counters wil not actually run until PMGC0[FAC] is cleared in
    pmc_start_ctrs(), so this will not reduce the effectiveness of PMM.

    Signed-off-by: Scott Wood
    Signed-off-by: Kumar Gala

    Scott Wood
     

19 May, 2009

1 commit

06 Feb, 2008

1 commit

  • 39aef685a   [POWERPC] Made FSL Book-E PMC support more generic ... Browse Code »

    Some of the more recent e300 cores have the same performance monitor
    implementation as the e500. e300 isn't book-e, so the name isn't
    really appropriate. In preparation for e300 support, rename a bunch
    of fsl_booke things to say fsl_emb (Freescale Embedded Performance Monitors).

    Signed-off-by: Andy Fleming
    Signed-off-by: Kumar Gala

    Andy Fleming