23 Feb, 2017
40 commits
-
User can specify clocks in devicetree which is used for accessing the registers
in this regmap.Signed-off-by: Dong Aisheng
(cherry picked from commit 4a89ef5b579e6fb5640df099ee13939ca6d3a325) -
According to clock framework, the clk_id could be NULL when getting clock.
But current code relies on a non null clk_id to get clock.
Changing the code to allow a null clk_id to get clock to make it more
reasonable to use.
And the regmap_mmio_gen_context will try to get clock by default but ignore
error if not finding the clock in case some regmap access not reply on
a specific clock.Signed-off-by: Dong Aisheng
(cherry picked from commit a60a38a5285ab27814f261ed39653c55a0a6e24b) -
Detailed reproduce steps:
1. boot-up to Linux command prompt .
2. Plug SD3.0 UHS-I SD Card into SD3 Connector (make sure SD Card running
at SD3.0 DDR50/1.8V).
2. write data to SD3 using "dd" command (SD3_CLK running at 1.8V/50MHz).
3. capture the SD3_CLK, SD3_DATA, SD3_CMD waveforms during data write using
FET probe (>=1GHz)
4. CLK waveforms like triangular wave are observed.HW team found that the pad setting of the SD3_CLK, SD3_DATA, SD3_CMD signal pins are
not optimized. In existing BSP, when running at SD3.0/DDR50/1.8V, SPEED/DSE/SRE
= 01/011/1 is used. They propose change it to -
SD3_CLK: SPEED/DSE/SRE = 01/110/1.
SD3_DATA/SD3_CMD: SPEED/DSE/SRE = 01/101/1.SDHC high speed cards also had such issue(refer to MLK-9500).
We only changed the default state (
(cherry picked from commit 69d4195c741050e0bc78d3005f8ff4f51990d1ae)Conflicts:
arch/arm/boot/dts/imx6sx-sdb.dts -
CAN devices are allocated to run on M4.
So do not touch CAN pads setting if M4 is enabled.Signed-off-by: Dong Aisheng
(cherry picked from commit 9d2605e51b9ba83382c5da3a838656c9910d75a1) -
Since CAN device is allocated to run on M4 and handled by M4 if M4 is enabled,
so we do not set CAN parent clock when M4 is enabled.Signed-off-by: Dong Aisheng
(cherry picked from commit 171a16fa6d62162e9c8cab38b9459e772c980d22) -
If is_enabled() is not defined in its ops, regulator core will assume
this regulator is already enabled, then we never can really enable it
after disabled.Signed-off-by: Li Jun
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Move FSL_UTP to be under USB_MASS_STORAGE since it depends on it.
Signed-off-by: Li Jun
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Revert "MLK-11623 ASoC: imx-cs42888: add 32k and 64k sample rate support"
This reverts commit 314a01f40599134086480ef3c5e89a54aeedbf1f.
In Async mode, record and playback use different samplerate, one is 32k,
another is 48kHz, there will be issue "unsupported sysclk ratio".example case is
arecord -Dhw:0,1 -f S16_LE -r 32000 -c 2 | aplay -f S16_LE -r 32000 -c 2Signed-off-by: Shengjiu Wang
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In suspend function, the complete will be set to done in callback.
After resuming, the convert will not spend time to wait the complete.
which is a wrong complete.
So in suspend function, the complete need to be reinited for next convert.Signed-off-by: Shengjiu Wang
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Set the imx rpmsg tests to be module in defaut.
Signed-off-by: Richard Zhu
(cherry picked from commit 20adce35ef6abfd6b0a52207febe069c7f09a1be) -
Since i.MX6SX, if USB vbus wake up is enabled, weak 2P5
needs to be on even if the DRAM is LPDDR2, previously, we need
to set stop_mode_config to keep 2P5 on, so enter DSM,
if USB vbus wakeup is enabled, we need to keep weak 2P5 on.Signed-off-by: Anson Huang
(cherry picked from commit 1ca4dffee79055ea95c59e27bab50bc5080310f5)
Signed-off-by: Peter Chen -
The GPC setting should be modified using the read-modify-update flow.
Signed-off-by: Bai Ping
-
It is better we disconnect (pulldown dp) host when the system enters
suspend if the host did not suspend bus beforehand, it can avoid
unnecessary udc suspend irq during usb enters suspend. This unexpected
suspend irq occurs due to the udc still pulls up dp, but the host
suspends bus due to it finds the device has disconnected. The device
turns off high speed terminal will be considered a disconnection event
from the host.It also fixes the bug ENGR00325724 describes.
Signed-off-by: Peter Chen
(cherry picked from commit 9d9ddd142cdbfb4bcbaae161a452596668441b1a) -
Set tx-d-cal to be 0x5 to improve usb signal quality.
Signed-off-by: Li Jun
-
Set tx-d-cal to be 0x5 to improve usb signal quality.
Signed-off-by: Li Jun
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Set tx-d-cal to be 0x5 to improve usb signal quality for all imx6qdl
sabresd boards.Signed-off-by: Li Jun
-
- Delete regulator-always-on for 3p0 since it needs to enable/disable
on the fly.
- Add "anatop-enable-bit" property as the offset of enable bit for
3p0, 1p1, and 2p5.
- USB PHY refers "reg_3p0" phandle at its node.Signed-off-by: Peter Chen
(cherry picked from commit c2c2cbc46fda3e8ea798d270a3410f351af9d1ca) -
When SMP is deselected, ARM_ARCH_TIMER is still enabled while
broadcast time is disabled, so when system enters WAIT mode,
ARM platform's clock will be disabled, then system tick timer
will stop and cause system stay at WAIT mode and timer event
will NOT come as expected.To fix this issue, we do runtime check in kernel boot up,
if SMP is NOT enabled, ARM_ARCH_TIMER will be disabled and
using GPT timer always.we have to put this check in early stage before common
arm_arch_timer driver probed.Signed-off-by: Anson Huang
-
As clock root does NOT have domain control on i.MX7D,
and the clock root gate does NOT consume much power,
so it is acceptable to leave clock root always enabled
when M4 is enabled, this is suggested by design team,
otherwise, need to use shared memory to control clk
root between A7 and M4, which is NOT friendly.Signed-off-by: Anson Huang
(cherry picked from commit bc4295b3aed83e426c49aa48f39224d2102048dd) -
i.MX7D TO1.1 updates the DDR script, ddr frequency scale flow
should be updated accordingly.Add runtime revision check to support both TO1.0 and TO1.1.
Signed-off-by: Anson Huang
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i.MX7D TO1.1 adds some DDR PHY register settings to fix the CKE
timing issue, when fast MIX off in DSM, need to restore them
to make sure the DDR PHY setting is correct.Signed-off-by: Anson Huang
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Design team recommend to put SCU/C0/C1 in same power up slot
to avoid reset timing issue of debug mode, adjust the power
up slot and timing per their requirement.Signed-off-by: Anson Huang
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Compared 'mux' against zero is meaningless. So correct this.
Signed-off-by: Fancy Fang
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The 'rgb' pointer may be dereferenced before being initialized.
So correct this.Signed-off-by: Fancy Fang
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The 'vmode' variable is used before it is initialized.
So initialize it before that.Signed-off-by: Fancy Fang
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The 'val' variable may be used before uninitialized.
So initialize it at the begining.Signed-off-by: Fancy Fang
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The 'timings' is allocated by 'of_get_display_timings()'
dynamically. So it should be freed when it is not used
anymore.Signed-off-by: Fancy Fang
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There may be potential memory leak when the 'desc' allocation failed.
The previous allocated descriptors should be freed when the allocation
failed.Signed-off-by: Fancy Fang
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Add imx6q/dl/qp sabresd, imx6sx sabreauto magic packet support.
Signed-off-by: Fugang Duan
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Originally we put all the definition of both imx7d normal pins and
lpsr pins in imx7d-pinfunc.h which may lead to a easy failure of
user by wrongly put the normal pins of &iomuxc under &iomuxc_lpsr
node due to user has no idea about the difference, then pinctrl
driver will take the wrong value to set which may potentially break
other devices to work.We have met this issue several times and it's hard to debug when it
happens.This patch separates the lpsr pins into a dedicated head file
to give user a reminder to put lpsr pins group under the correct
pinctrl device node.Signed-off-by: Dong Aisheng
(cherry picked from commit c524454c24fd9e5e329351dd154cbd24d47d0e0e) -
pinmux settings using GPIO1_IO0[0-7] should use iomuxc_lpsr,
but not iomuxc. If use iomuxc, you will set wrong register
and may impact other functions.Without this patch, SAI3_MCLK use GPIO1_IO03 pinmux and impacts
QSPI function.Signed-off-by: Peng Fan
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Add sensor node in 6sx-ard dts. The sensors are mma8451,
mag3110 and isl29023.Signed-off-by: Gao Pan
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ARM does NOT execute one instruction every cycle, the bus bandwidth,
cache status etc. would impacts the instruction execution time, so we
can NOT just calculate the delay time by ARM frequency, this patch
adjusts loop number to get a ~20us delay, measured via GPIO pin.Signed-off-by: Anson Huang
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Per design team's recommendation, for i.MX7D TO1.1
LPSR mode, as IOMUXC will lost power, so it needs to
use TO1.0's flow to avoid CKE toggle during retention,
but it has a limitation of POR reset fail during LPSR.Signed-off-by: Anson Huang
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Dereference null return value (NULL_RETURNS).
Signed-off-by: Robin Gong
(cherry picked from commit e5d41f4bbded2f2b948a13d4dc04596cd896b072) -
l2c210_flush_all, the underlying implementation of outer_flush_all() has the
constraint on 4.1 kernel that, it can not be called under interrupt context.
However the EPDC driver can not guarantee this condition at calling point, thus
it could cause kernel dump. This has been observed on i.MX6SL, and theorically
on other platforms like i.MX6DL (using PL310 L2 cache). So use outer_flush_range
to fix it.Although we don't have such issue on i.MX7D (not PL310 L2), we still prefer to
use outer_flush_range() for legacy software dithering support and for easy
maintenance. Then we do the change in both EPDC driver.------------[ cut here ]------------
Kernel BUG at 800204d8 [verbose debug info unavailable]
Internal error: Oops - BUG: 0 [#1] PREEMPT SMP ARM
Modules linked in: galcore(O) evbug
CPU: 0 PID: 842 Comm: kworker/u3:1 Tainted: G O 4.1.8-1.0.0+ge352a0b #1
Hardware name: Freescale i.MX6 SoloLite (Device Tree)
Workqueue: EPDC Submit epdc_submit_work_func
task: a8a8f900 ti: a92a4000 task.ti: a92a4000
PC is at l2c210_flush_all+0x5c/0x60
LR is at epdc_submit_work_func+0x684/0xbf8
pc : [] lr : [] psr: 600b0013
sp : a92a5e90 ip : a9150c8c fp : a8480518
r10: a84a28c0 r9 : 00000008 r8 : a9150644
r7 : a91512e0 r6 : 0000012c r5 : a91512e0 r4 : a91512dc
r3 : a00b0013 r2 : 80b184a0 r1 : 701fe019 r0 : f4a02000
Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
Control: 10c53c7d Table: a943404a DAC: 00000015
Process kworker/u3:1 (pid: 842, stack limit = 0xa92a4210)
Stack: (0xa92a5e90 to 0xa92a6000)
5e80: a92a5ed0 8005d058 0000bbc2 a851d4c0
5ea0: 00000000 a9150000 a8480000 a8480440 00000190 00000193 55555556 a84a28c0
5ec0: a8480518 a8500000 80b18088 a94f3900 00000000 00000000 00000190 0000012c
5ee0: a94f3900 a8480518 a87e8d80 a8479000 a845a200 00000020 00000000 a8479000
5f00: a8479000 80046458 a92a4000 a8479000 a8479014 a8479000 a87e8d98 a8479014...
Signed-off-by: Robby Cai
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Fix mxc cec driver potential memory leak issue.
Signed-off-by: Sandor Yu
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unregister the busfreq_notifier when the thermal driver is removed.
Signed-off-by: Bai Ping
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On v4.1, use syscon-poweroff driver instead of poweroff interface in
rtc-snvs driver.Signed-off-by: Robin Gong
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enable snvs-poweroff driver on imx6sx(except sabreauto board),imx6ul and
imx7d all boards.Signed-off-by: Robin Gong