03 May, 2011
2 commits
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Signed-off-by: Anatolij Gustschin
Cc: Li Yang
Signed-off-by: Greg Kroah-Hartman -
Signed-off-by: Anatolij Gustschin
Signed-off-by: Greg Kroah-Hartman
23 Oct, 2010
2 commits
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this patch gives the possibility to workaround bug ENGcm09152
on i.MX35 when the hardware workaround is also implemented on
the board.
It covers the workaround described on page 25 of the following Errata :
http://cache.freescale.com/files/dsp/doc/errata/IMX35CE.pdfSigned-off-by: Eric Bénard
Signed-off-by: Greg Kroah-Hartman -
Extends FSL EHCI platform driver glue layer to support
MPC5121 USB controllers. MPC5121 Rev 2.0 silicon EHCI
registers are in big endian format. The appropriate flags
are set using the information in the platform data structure.
MPC83xx system interface registers are not available on
MPC512x, so the access to these registers is isolated in
MPC512x case. Furthermore the USB controller clocks
must be enabled before 512x register accesses which is
done by providing platform specific init callback.The MPC512x internal USB PHY doesn't provide supply voltage.
For boards using different power switches allow specifying
DRVVBUS and PWR_FAULT signal polarity of the MPC5121 internal
PHY using "fsl,invert-drvvbus" and "fsl,invert-pwr-fault"
properties in the device tree USB nodes. Adds documentation
for this new device tree bindings.Signed-off-by: Anatolij Gustschin
Cc: Grant Likely
Signed-off-by: Greg Kroah-Hartman
24 Nov, 2009
1 commit
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Commit 87ec0e98cfdd8b68da6a7f9e70142ffc0e404fbb in kumar's next branch
broke one of my test configs since it looks like Anton forgot about
that mpc832x_rdb platform which still uses the old style probing for
the SPI stuff.I'll let them do a cleaner fix that probably involves changing the
probing method and getting rid of the platform device but for now
this will do to fix it.Signed-off-by: Benjamin Herrenschmidt
12 Nov, 2009
2 commits
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Export is needed for modular builds, and a static inline stub is needed
for non-MPC83xx builds.Signed-off-by: Anton Vorontsov
Signed-off-by: Kumar Gala -
Soon there will be more flags introduced in subsequent patches, so
let's turn qe_mode into flags.Also introduce mpc8xxx_spi_strmode() and print current SPI mode.
Signed-off-by: Anton Vorontsov
Acked-by: David Brownell
Signed-off-by: Kumar Gala
19 Jun, 2009
1 commit
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mpc52xx_psc_spi driver is the last user of the legacy activate_cs and
deactivate_cs callbacks, so convert the driver to the cs_control hook and
remove the legacy callbacks from fsl_spi_platform_data struct.Signed-off-by: Anton Vorontsov
Cc: Grant Likely
Cc: David Brownell
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
22 Apr, 2009
1 commit
16 Apr, 2009
1 commit
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In commit 364fdbc00fbdd409ade63500710123fe323aa164 ("spi_mpc83xx:
rework chip selects handling"), I merged activate_cs and deactivate_cs
hooks into cs_control, but I overlooked that mpc52xx_psc_spi driver
is using these hooks too. And that resulted in the following build
failure:CC drivers/spi/mpc52xx_psc_spi.o
drivers/spi/mpc52xx_psc_spi.c: In function 'mpc52xx_psc_spi_do_probe':
drivers/spi/mpc52xx_psc_spi.c:398: error: 'struct fsl_spi_platform_data'
has no member named 'activate_cs'
drivers/spi/mpc52xx_psc_spi.c:399: error: 'struct fsl_spi_platform_data'
has no member named 'deactivate_cs'
make[2]: *** [drivers/spi/mpc52xx_psc_spi.o] Error 1This patch simply adds the legacy hooks back for 2.6.30, and for
2.6.31 we'll convert the driver to ->cs_control.Reported-by: Subrata Modak
Signed-off-by: Anton Vorontsov
Signed-off-by: Grant Likely
08 Apr, 2009
1 commit
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This patch documents the new bindings for the MPC I2C bus driver.
Furthermore, it removes obsolete FSL device related definitions
for I2C.Signed-off-by: Wolfgang Grandegger
Signed-off-by: Kumar Gala
07 Apr, 2009
1 commit
01 Apr, 2009
2 commits
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Implement full support for OF SPI bindings. Now the driver can manage its
own chip selects without any help from the board files and/or fsl_soc
constructors.The "legacy" code is well isolated and could be removed as time goes by.
Signed-off-by: Anton Vorontsov
Cc: David Brownell
Cc: Benjamin Herrenschmidt
Cc: Kumar Gala
Cc: Grant Likely
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds -
The main purpose of this patch is to pass 'struct spi_device' to the chip
select handling routines. This is needed so that we could implement
full-fledged OpenFirmware support for this driver.While at it, also:
- Replace two {de,activate}_cs routines by single cs_contol().
- Don't duplicate platform data callbacks in mpc83xx_spi struct.Signed-off-by: Anton Vorontsov
Cc: David Brownell
Cc: Benjamin Herrenschmidt
Cc: Kumar Gala
Cc: Grant Likely
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
31 Mar, 2009
1 commit
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Remove old artifacts leftover from the platform driver gianfar and
fsl_i2c drivers. These symbols became unused when the drivers
were migrated over to use the of_platform bus.Signed-off-by: Grant Likely
Signed-off-by: Kumar Gala
17 Dec, 2008
1 commit
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Does the same for the accompanying MDIO driver, and then modifies the TBI
configuration method. The old way used fields in einfo, which no longer
exists. The new way is to create an MDIO device-tree node for each instance
of gianfar, and create a tbi-handle property to associate ethernet controllers
with the TBI PHYs they are connected to.Signed-off-by: Andy Fleming
Signed-off-by: David S. Miller
31 Oct, 2008
1 commit
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The init_phy() function attaches to the PHY, then configures the
SerDesTBI link (in SGMII mode). The TBI is on the MDIO bus with the PHY
(sort of) and is accessed via the gianfar's MDIO registers, using the
functions gfar_local_mdio_read/write(), which don't do any locking.The previously attached PHY will start a work-queue on a timer, and
probably an irq handler as well, which will talk to the PHY and thus use
the MDIO bus. This uses phy_read/write(), which have locking, but not
against the gfar_local_mdio versions.The result is that PHY code will try to use the MDIO bus at the same time
as the SerDes setup code, corrupting the transfers.Setting up the SerDes before attaching to the PHY will insure that there is
no race between the SerDes code and *our* PHY, but doesn't fix everything.
Typically the PHYs for all gianfar devices are on the same MDIO bus, which
is associated with the first gianfar device. This means that the first
gianfar's SerDes code could corrupt the MDIO transfers for a different
gianfar's PHY.The lock used by phy_read/write() is contained in the mii_bus structure,
which is pointed to by the PHY. This is difficult to access from the
gianfar drivers, as there is no link between a gianfar device and the
mii_bus which shares the same MDIO registers. As far as the device layer
and drivers are concerned they are two unrelated devices (which happen to
share registers).Generally all gianfar devices' PHYs will be on the bus associated with the
first gianfar. But this might not be the case, so simply locking the
gianfar's PHY's mii bus might not lock the mii bus that the SerDes setup
code is going to use.We solve this by having the code that creates the gianfar platform device
look in the device tree for an mdio device that shares the gianfar's
registers. If one is found the ID of its platform device is saved in the
gianfar's platform data.A new function in the gianfar mii code, gfar_get_miibus(), can use the bus
ID to search through the platform devices for a gianfar_mdio device with
the right ID. The platform device's driver data is the mii_bus structure,
which the SerDes setup code can use to lock the current bus.Signed-off-by: Trent Piepho
CC: Andy Fleming
Signed-off-by: Jeff Garzik
17 Jul, 2008
2 commits
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Signed-off-by: Scott Wood
Signed-off-by: Kumar Gala -
Basic PM support for 83xx. Standby is implemented as sleep.
Suspend-to-RAM is implemented as "deep sleep" (with the processor
turned off) on 831x.Signed-off-by: Scott Wood
Signed-off-by: Kumar Gala
30 Apr, 2008
1 commit
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Remove the "#ifdef __KERNEL__" tests from unexported header files in
linux/include whose entire contents are wrapped in that preprocessor
test.Signed-off-by: Robert P. J. Day
Cc: David Woodhouse
Cc: Sam Ravnborg
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
17 Apr, 2008
1 commit
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Having the id field be an int was making more complex bus topologies
excessively difficult. For now, just convert it to a string, and
change all instances of "bus->id = val" to
snprintf(id, MII_BUS_ID_LEN, "%x", val).Signed-off-by: Andy Fleming
Signed-off-by: Jeff Garzik
19 Jul, 2007
1 commit
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The TSEC/eTSEC can detect the interface to the PHY automatically,
but it isn't able to detect whether the RGMII connection needs internal
delay. So we need to detect that change in the device tree, propagate
it to the platform data, and then check it if we're in RGMII. This fixes
a bug on the 8641D HPCN board where the Vitesse PHY doesn't use the delay
for RGMII.Signed-off-by: Andy Fleming
18 Jul, 2007
1 commit
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Quicc Engine enabled mpc83xx CPU's has a somewhat different HW interface to
the SPI controller. This patch adds a qe_mode knob that sees to that
needed adaptions are performed.Signed-off-by: Joakim Tjernlund
Signed-off-by: David Brownell
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
10 Jul, 2007
1 commit
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Adds support for PowerQuicc on-chip PCMCIA. The driver is implemented as
of_device, so only arch/powerpc stuff is capable to use it, which now implies
only mpc885ads reference board.To cope with the code that should be hooked inside driver, but is really board
specific (like set_voltage), global structure mpc8xx_pcmcia_ops holds
necessary function pointers that are filled in the BSP code.[akpm@linux-foundation.org: whitespace diddles]
Signed-off-by: Vitaly Bordug
Acked-by: Arnd Bergmann
Acked-by: Olof Johansson
Cc: Dominik Brodowski
Cc: Paul Mackerras
Cc: Benjamin Herrenschmidt
Signed-off-by: Andrew Morton
Signed-off-by: Kumar Gala
28 Apr, 2007
1 commit
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migrate ucc_geth to use the common phylib code.
There are several side effects from doing this:
o deprecate 'interface' property specification present
in some old device tree source files in
favour of a split 'max-speed' and 'interface-type'
description to appropriately match definitions
in include/linux/phy.h. Note that 'interface' property
is still honoured if max-speed or interface-type
are not present (backward compatible).
o compile-time CONFIG_UGETH_HAS_GIGA is eliminated
in favour of probe time speed derivation logic.
o adjust_link streamlined to only operate on maccfg2
and upsmr.r10m, instead of reapplying static initial
values related to the interface-type.
o Addition of UEC MDIO of_platform driver requires
platform code add 'mdio' type to id list
prior to calling of_platform_bus_probe (separate patch).
o ucc_struct_init introduced to reduce ucc_geth_startup
complexity.Signed-off-by: Li Yang
Signed-off-by: Kim Phillips
Signed-off-by: Jeff Garzik
11 Dec, 2006
1 commit
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PHY_POLL is defined in include it in so
board code will have it defined.Signed-off-by: Kumar Gala
04 Oct, 2006
1 commit
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Add QUICC Engine (QE) configuration, header files, and
QE management and library code that are used by QE devices
drivers.Includes Leo's modifications up to, and including, the
platform_device to of_device adaptation:"The series of patches add generic QE infrastructure called
qe_lib, and MPC8360EMDS board support. Qe_lib is used by
QE device drivers such as ucc_geth driver.This version updates QE interrupt controller to use new irq
mapping mechanism, addresses all the comments received with
last submission and includes some style fixes.v2: Change to use device tree for BCSR and MURAM;
Remove I/O port interrupt handling code as it is not generic
enough.v3: Address comments from Kumar; Update definition of several
device tree nodes; Copyright style change."In addition, the following changes have been made:
o removed typedefs
o uint -> u32 conversions
o removed following defines:
QE_SIZEOF_BD, BD_BUFFER_ARG, BD_BUFFER_CLEAR, BD_BUFFER,
BD_STATUS_AND_LENGTH_SET, BD_STATUS_AND_LENGTH, and BD_BUFFER_SET
because they hid sizeof/in_be32/out_be32 operations from the reader.
o fixed qe_snums_init() serial num assignment to use a const array
o made CONFIG_UCC_FAST select UCC_SLOW
o reduced NR_QE_IC_INTS from 128 to 64
o remove _IO_BASE, etc. defines (not used)
o removed irrelevant comments, added others to resemble removed BD_ defines
o realigned struct definitions in headers
o various other style fixes including things like pinMask -> pin_mask
o fixed a ton of whitespace issues
o marked ioregs as __be32/__be16
o removed platform_device code and redundant get_qe_base()
o removed redundant comments
o added cpu_relax() to qe_reset
o uncasted all get_property() assignments
o eliminated unneeded casts
o eliminated immrbar_phys_to_virt (not used)Signed-off-by: Li Yang
Signed-off-by: Shlomi Gridish
Signed-off-by: Kim Phillips
Signed-off-by: Paul Mackerras
22 May, 2006
1 commit
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This driver supports the SPI controller on the MPC83xx SoC devices from
Freescale. Note, this driver supports only the simple shift register SPI
controller and not the descriptor based CPM or QUICCEngine SPI controller.Signed-off-by: Kumar Gala
Signed-off-by: David Brownell
Cc: Greg KH
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
21 Mar, 2006
1 commit
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Adding a Host Mode USB driver for the Freescale 83xx.
This driver supports both the Dual-Role (DR) controller and the
Multi-Port-Host (MPH) controller present in the Freescale MPC8349. It has
been tested with the MPC8349CDS reference system. This driver depends on
platform support code for setting up the pins on the device package in a
manner appropriate for the board in use. Note that this patch requires
selecting the EHCI controller option under the USB Host menu.Signed-off-by: Randy Vinson
Signed-off-by: Greg Kroah-Hartman
13 Jan, 2006
2 commits
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Make the driver produce the string used by phy_connect and have board specific
code pass the integer mii bus id and phy device id for the specific controller
instance.Signed-off-by: Kumar Gala
Signed-off-by: Andrew Morton
Signed-off-by: Jeff Garzik -
We can now have the gianfar mii platform device have a proper resource for the
IO memory region for its registers. Previously we passed this information
that the platform_data structure because we couldn't handle overlapping memory
regions for platform devices.Signed-off-by: Kumar Gala
Signed-off-by: Andrew Morton
Signed-off-by: Jeff Garzik
14 Nov, 2005
1 commit
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Changed jobs and the Freescale address is no longer valid.
Signed-off-by: Kumar Gala
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
29 Oct, 2005
1 commit
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This patch updates the 85xx platform code to support the new PHY Layer.
Signed-off-by: Andy Fleming
Signed-off-by: Kumar Gala
Signed-off-by: Andrew Morton
Signed-off-by: Paul Mackerras
22 Jun, 2005
1 commit
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Added descriptions of the new MPC8548 family processors, e500 core and
peripherals.Signed-off-by: Kumar Gala
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
17 Apr, 2005
1 commit
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Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.Let it rip!
