05 Nov, 2014

2 commits

  • The ADC on exynos7 is quite similar to ADCv2. The differences are as
    follows:
    - exynos7-adc has 8 input channels (as against 10 in ADCv2).
    - exynos7 does not include an ADC PHY control register.
    - Some ADC_CON2 register bits being used in ADCv2 are listed as
    reserved in exynos7-adc. This results in a different init_hw
    function for exynos7.

    Signed-off-by: Abhilash Kesavan
    Reviewed-by: Chanwoo Choi
    Signed-off-by: Jonathan Cameron

    Abhilash Kesavan
     
  • This patch updates the IIO based ADC driver to use syscon and regmap
    APIs to access and use PMU registers instead of remapping the PMU
    registers in the driver.

    Signed-off-by: Naveen Krishna Chatradhi
    To: linux-iio@vger.kernel.org
    Acked-by: Kukjin Kim
    Signed-off-by: Jonathan Cameron

    Naveen Krishna Chatradhi
     

27 Aug, 2014

1 commit


08 Aug, 2014

2 commits

  • This patch add support for s3c2410/s3c2416/s3c2440/s3c2443 ADC. The s3c24xx
    is alomost same as ADCv1. But, There are a little difference as following:
    - ADCMUX register address
    - ADCDAT mask (10 bit or 12 bit ADC resolution according to SoC version)
    - s3c24xx/s3c64xx has not included ADC_PHY enable register

    Signed-off-by: Chanwoo Choi
    Acked-by: Arnd Bergmann
    Signed-off-by: Jonathan Cameron

    Chanwoo Choi
     
  • The ADC in s3c64xx is almost the same as exynosv1, but
    has a different 'select' method. Adding this here will be
    helpful to move over the existing s3c64xx platform from the
    legacy plat-samsung/adc driver to the new exynos-adc.

    Signed-off-by: Arnd Bergmann
    Signed-off-by: Chanwoo Choi
    Signed-off-by: Jonathan Cameron

    Arnd Bergmann
     

24 Jul, 2014

2 commits

  • This patch control special clock for ADC in Exynos series's FSYS block.
    If special clock of ADC is registerd on clock list of common clk framework,
    Exynos ADC drvier have to control this clock.

    Exynos3250/Exynos4/Exynos5 has 'adc' clock as following:
    - 'adc' clock: bus clock for ADC

    Exynos3250 has additional 'sclk_adc' clock as following:
    - 'sclk_adc' clock: special clock for ADC which provide clock to internal ADC

    Exynos 4210/4212/4412 and Exynos5250/5420 has not included 'sclk_adc' clock
    in FSYS_BLK. But, Exynos3250 based on Cortex-A7 has only included 'sclk_adc'
    clock in FSYS_BLK.

    Signed-off-by: Chanwoo Choi
    Acked-by: Kyungmin Park
    Reviewed-by: Tomasz Figa
    Acked-by: Arnd Bergmann
    Signed-off-by: Jonathan Cameron

    Chanwoo Choi
     
  • This patchset add 'exynos_adc_data' structure which includes some functions
    to control ADC operation and specific data according to ADC version (v1 or v2).

    Signed-off-by: Chanwoo Choi
    Acked-by: Kyungmin Park
    Reviewed-by: Naveen Krishna Chatradhi
    Reviewed-by: Tomasz Figa
    Acked-by: Arnd Bergmann
    Signed-off-by: Jonathan Cameron

    Chanwoo Choi
     

22 May, 2014

1 commit


01 May, 2014

4 commits


26 Apr, 2014

1 commit

  • Using pdev->dev with device_for_each_child() would iterate over all
    of the children of the platform device and delete them.
    Thus, causing crashes during module unload.

    We should be using the indio_dev->dev structure for
    registering/unregistering child nodes.

    Reported-by: Doug Anderson
    Signed-off-by: Naveen Krishna Ch
    Reviewed-by: Doug Anderson
    Tested-by: Doug Anderson
    Signed-off-by: Jonathan Cameron

    Naveen Krishna Ch
     

04 Aug, 2013

1 commit


27 May, 2013

1 commit


23 May, 2013

2 commits


29 Mar, 2013

1 commit


18 Mar, 2013

2 commits


16 Mar, 2013

1 commit