10 Feb, 2015
3 commits
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The register ASRCFG is volatile, but some bits need to be recovered
after suspend/resume.Signed-off-by: Shengjiu Wang
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Merged from 2a17c1bbcd83a9d9f6d07bc0545742a59a043ae4
The SDMA driver doesn't support DMA_PAUSE and DMA_RESUME commands.
So this patch use TRIGGER_START for TRIGGER_RESUME and TRIGGER_SUSPEND
for TRIGGER_STOP as a work around so that Audio can normally stop
and restart its corresponding DMA channels.Signed-off-by: Shengjiu Wang
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The register SFCSR is volatile, but some bits in it need to be
recovered after suspend/resume.Signed-off-by: Shengjiu Wang
16 Jan, 2015
37 commits
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The 'big-endian-data' property is originally used to indicate whether the
LSB firstly or MSB firstly will be transmitted to the CODEC or received
from the CODEC, and there has nothing relation to the memory data.Generally, if the audio data in big endian format, which will be using the
bytes reversion, Here this can only be used to bits reversion.So using the 'lsb-first' instead of 'big-endian-data' can make the code
to be readable easier and more easy to understand what this property is
used to do.This property used for configuring whether the LSB or the MSB is transmitted
first for the fifo data.Signed-off-by: Xiubo Li
Acked-by: Nicolin Chen
Signed-off-by: Mark Brown
(cherry picked from commit eadb0019d206591e34e864b62059b292e157d8fc) -
Signed-off-by: Xiubo Li
Signed-off-by: Mark Brown
(cherry picked from commit 014fd22ef9c6a7e9536b7e16635714a1a34810a8) -
Write initial words to SAI FIFO to reduce underrun error
Signed-off-by: Shengjiu Wang
(cherry picked from commit 7ba8ae883d84540fac5ed4147d124399537bc0b3) -
We must ensure that the clocking configuration is valid as rapidly as possible.
And do software reset before the others registers updates, or the registers
will be reset to the default state.Signed-off-by: Zidan Wang
Signed-off-by: Mark Brown
(cherry picked from commit 3ad5e861a715cbe932cd145d4612c11e5912a72f) -
Set the CODEC driver's suspend_bias_off flag rather than manually going to
SND_SOC_BIAS_OFF in suspend and SND_SOC_BIAS_STANDBY in resume. This makes
the code a bit shorter and cleaner.Since the ASoC core now takes care of setting the bias level to
SND_SOC_BIAS_OFF when removing the CODEC there is no need to do it manually
anymore either.The manual transition to SND_SOC_BIAS_STANDBY at the end of CODEC probe()
can also be removed as the core will automatically do this after the CODEC
has been probed.Signed-off-by: Lars-Peter Clausen
Acked-by: Charles Keepax
Signed-off-by: Mark Brown
(cherry picked from commit 0a87a6e1c09c3b93d91bf65809e79cf6cf358785) -
Document the device tree binding for the WM8960 codec, and modify the
driver to extract the platform data from device tree, if present.Signed-off-by: Zidan Wang
Signed-off-by: Mark Brown
(cherry picked from commit e2280c9040d8bc5039617af35ccf7b8ac4abb428) -
If there is no codec device, the machine driver will not register the
card. then alsa will not return RETRY error. update the error handling
for machine driver.Signed-off-by: Shengjiu Wang
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For p2p output, the output divider should align with the output sample
rate, if use the Ideal sample rate, there will be a lot of overload, which
will cause underrun.Signed-off-by: Shengjiu Wang
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Merged from 49108fcf7b79ed77d34be33b53a3964b2ac27204
1. Watermark level in sdma use byte as its unit. but asrc driver use
word, there is mismatch between them. Here fix this issue and sdma can
work more efficiency.
2. Enlarge the larst_period_size, when use small size, for some case,
the dma task will timeout, because sdma has no much data for output.Signed-off-by: Shengjiu Wang
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merge 7e1a620a030d17f93fdd97d076f1cdd042e79337
The reason of crach is that some variables are not protected in
function mxc_asrc_suspend(), when suspend, there is possibility to
access one NULL pointer.
Refine the spin lock usage, add protecting for pair_hold.Signed-off-by: Shengjiu Wang
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Merge from c086d0151ee3e131b52bef96c5096d1ee603c852
Return value -ERESTARTSYS is not visible for user space according
to include/linux/errno.h. So use -EBUSY replace it.Signed-off-by: Shengjiu Wang
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The latest asrc's channel bits is 4, bit the old asrc's channel bits is 3.
So here add protection for when using the old version asrc.Signed-off-by: Shengjiu Wang
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The default setting of sai is RX sync with TX, TX output the I2S clock. So
When recording, we should set TCR2's divider, not RCR2's divider.Signed-off-by: Shengjiu Wang
(cherry picked from commit 9bfe1d33b984b44af011c644f995c3b406b2f3e1) -
The bclk caculation should according to the slot num, not the channels.
Because sometime we have two slots, but only one slot is enabled for mono
channel.
As when the codec wm8962 works on mono mode, it needs two slots I2S signal.
So here set the default slots of sai to 2, and add function set_tdm_slots for
future usage.Signed-off-by: Shengjiu Wang
(cherry picked from commit 991a1f269ce4e4d0daa2cf5615169891acca0607) -
Adds .ignore_pmdown_time = true to codec driver struct.
HDMI codec is currently a dummy codec and doesn't benefit from pmdown
delay. Even if in the future the codec would controll HDMI encoder, it
would still be a digital to digital interface that should have no need
for pmdown delay.Signed-off-by: Jyri Sarha
Signed-off-by: Mark Brown
(cherry picked from commit 69434097916bc52a4d6d495a0d719eb02e0cff9e) -
HDMI audio can not have more than 24 bits even if on i2s bus there
would be 32 bit samples. Mark this by adding .sig_bits = 24 to
playback stream definition.Signed-off-by: Jyri Sarha
Signed-off-by: Mark Brown
(cherry picked from commit 74d813cf37c210e94d155b0c19598fe269b8f78c) -
Implement machine driver for mqs, which use the sai as cpu dai.
sai work on master mode.Signed-off-by: Shengjiu Wang
(cherry picked from commit cac9eb41debc6444d753dc936cdf76874260b9e4) -
Implement codec driver for mqs. mqs is a very simple IP. which support:
Word length: 16bit.
DAI format: Left-Justified, slave mode.Signed-off-by: Shengjiu Wang
(cherry picked from commit 9da6bdd2072b850e9bb910512123eff7d80a0e2f) -
After several open/close sai test with ctrl+c, there will be I/O error.
The SAI can't work anymore, can't recover. There will be no frame clock.
With adding the software reset in trigger stop, the issue can be fixed.Signed-off-by: Shengjiu Wang
(cherry picked from commit 5e74f9510104df33b7c85f266f6e017428277047) -
SAI has 4 mclk source, and the divider is 8bit. fsl_sai_set_bclk will
select proper mclk source and calculate the divider.
After fsl_sai_set_bclk, enable the selected mclk in hw_params(), and
add hw_free() to disable the mclk.Signed-off-by: Shengjiu Wang
(cherry picked from commit 6dc915199870f692c41f6694557e281d61bc9207) -
There is one design rule according to SAI's reference manual:
If the transmitter bit clock and frame sync are to be used by both transmitter
and receiver, the transmitter must be configured for asynchronous operation
and the receiver for synchronous operation.And SYNC of TCR2 is a 2-width control bit:
00 Asynchronous mode.
01 Synchronous with receiver.
10 Synchronous with another SAI transmitter.
11 Synchronous with another SAI receiver.So the driver should have set SYNC bit of TCR2 to 0x0, and meanwhile set SYNC
bit of RCR2 to 0x1 (Synchronous with transmitter).Signed-off-by: Nicolin Chen
Signed-off-by: Mark Brown
(cherry picked from commit 855675f6e6a65688a7f4cf45b9b5a98cf6c6f5c3) -
The previous patch (ASoC: fsl_sai: Add asynchronous mode support) added
new Device Tree bindings for Asynchronous and Synchronous modes support.
However, these two shall not be present at the same time.So this patch just simply makes them exclusive so as to avoid incorrect
Device Tree binding usage.Signed-off-by: Nicolin Chen
Signed-off-by: Mark Brown
(cherry picked from commit ce7344a4ebabe90e064d3e087727f45624cdc942) -
SAI supports these operation modes:
1) asynchronous mode
Both Tx and Rx are set to be asynchronous.
2) synchronous mode (Rx sync with Tx)
Tx is set to be asynchronous, Rx is set to be synchronous.
3) synchronous mode (Tx sync with Rx)
Rx is set to be asynchronous, Tx is set to be synchronous.
4) synchronous mode (Tx/Rx sync with another SAI's Tx)
5) synchronous mode (Tx/Rx sync with another SAI's Rx)* 4) and 5) are beyond this patch because they are related with another SAI.
As the initial version of this SAI driver, it supported 2) as default while
the others were totally missing.So this patch just adds supports for 1) and 3).
Signed-off-by: Nicolin Chen
Signed-off-by: Mark Brown
(cherry picked from commit 08fdf65e37d560581233e06a659f73deeb3766f9) -
There is one design rule according to SAI's reference manual:
If the transmitter bit clock and frame sync are to be used by both transmitter
and receiver, the transmitter must be configured for asynchronous operation
and the receiver for synchronous operation.And SYNC of TCR2 is a 2-width control bit:
00 Asynchronous mode.
01 Synchronous with receiver.
10 Synchronous with another SAI transmitter.
11 Synchronous with another SAI receiver.So the driver should have set SYNC bit of TCR2 to 0x0, and meanwhile set SYNC
bit of RCR2 to 0x1 (Synchronous with transmitter).Signed-off-by: Nicolin Chen
Signed-off-by: Mark Brown
(cherry picked from commit af96ff5b7448dc776dc24a5c4313c6ec1ee94e53) -
This patch adds software reset code in dai_probe() so as to make a true init
by clearing SAI's internal logic, including the bit clock generation, status
flags, and FIFO pointers.Signed-off-by: Nicolin Chen
Signed-off-by: Mark Brown
(cherry picked from commit 376d1a92ca587d3974d4791cdb99baa8b8e7f0dd) -
Configure the aumux port to output SRCK and SRFS from STCK and STFS
of internal port when use the SYN mode.Signed-off-by: Shengjiu Wang
(cherry picked from commit f4428f5617916863b5410afea5614cc52190f1a8) -
As the codec_name has a suffix, which is a index and is different
for different platform or different kernel. So here change machine driver
to use codec_of_node, which can be same for different platform/kernel,
then we can maintain a same machine driver for fm.Signed-off-by: Shengjiu Wang
(cherry picked from commit e87b135f34cba5cfcd0614b045d4035118fb6d77) -
In the frame_to_bytes(), when hw_ptr*frame_bits exceed the maxmum of unsigned
long, the return value is saturated, so the appl_bytes is wrong.
This patch is to correct the usage of frame_to_bytes().Signed-off-by: Shengjiu Wang
(cherry picked from commit 9e66132d9c96305b65aa5fa3ba8a35271a04ded9) -
There is very low possibility that channel swap happened in beginning when
multi output/input pin is enabled. The issue is that hardware can't send data
to correct pin in the begginning with the normal enable flow.
Here use TSMA/TSMB as the trigger for sending data to workaround this issue.Signed-off-by: Shengjiu Wang
(cherry picked from commit 859b0fc4544bef30e269b4f6a81999db1d07a42d) -
When test with case arecord -Dhw:0,1 | aplay -Dhw:0,0, xrun happened,
the reset handler will be called, but for BE(backend) stream, the
substream->ops is null.
This patch is to fix this null pointer issue.Signed-off-by: Shengjiu Wang
(cherry picked from commit 4db112a8cd3caf5a553afea88cf7fe8d9781f459) -
The current imx-sgtl5000 driver always attaches the cpu-dai to ssi while
in fact it could be attached to other cpu-dais like SAI. Thus this patch
use a general code to support another cpu-dai. And meanwhile update the
devicetree for i.MX6 Series.Acked-by: Wang Shengjiu
Signed-off-by: Nicolin Chen
(cherry picked from commit cb5dfaf44d2fdbce4329c2e4762e8450c8cd3b3c) -
The SRPC register should be volatile, LOCK bit is set by the hardware.
Signed-off-by: Shengjiu Wang
(cherry picked from commit 35ac9096cbe158962e779fd9bc64aeb74abbc745) -
Not only SIS but also other read-only or write-only reigsters should be marked
as volatile register so as not to let regcache cache them. So this patch just
adds those missing registers.Signed-off-by: Nicolin Chen
(cherry picked from commit 56ad235ba23274fc05422ad4b13153d1c56801c4) -
For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of
modules during system suspend and resume procedure. Thus, AUDMUX needs to
save all the values of registers before the system suspend and restore them
after the system resume.Acked-by: Wang Shengjiu
Signed-off-by: Nicolin Chen
(cherry picked from commit 3f3781143ba2800f7e3e46dbecc0c7a76d22a146) -
For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of
modules during system suspend and resume procedure. Thus, SSI needs to save
all the values of registers before the system suspend and restore them after
the system resume.Acked-by: Wang Shengjiu
Signed-off-by: Nicolin Chen
(cherry picked from commit 34c50abd9df28580b367070bc20b8bca6cd7655c) -
For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of
modules during system suspend and resume procedure. Thus, SPDIF needs to save
all the values of registers before the system suspend and restore them after
the system resume.Acked-by: Wang Shengjiu
Signed-off-by: Nicolin Chen
(cherry picked from commit fd7d2c1a137c1b9d7adb58aaf06b90938172b964) -
For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of
modules during system suspend and resume procedure. Thus, ESAI needs to save
all the values of registers before the system suspend and restore them after
the system resume.Acked-by: Wang Shengjiu
Signed-off-by: Nicolin Chen
(cherry picked from commit fc69de0b0cc1d9a85ad7f7363da6dec02945964a)
