12 Apr, 2022
1 commit
05 Apr, 2022
1 commit
29 Apr, 2019
1 commit
03 Apr, 2019
1 commit
12 Mar, 2018
3 commits
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Signed-off-by: Antoine Bouyer
(cherry picked from commit 642119b966e25a6a6606460470b0def9418647ae) -
These pointers are required for drm dts
Signed-off-by: Antoine Bouyer
(cherry picked from commit 5f048351c272121cb82481a680407c415a898b3e) -
Add a dedicated DSD512 pinmux group for DSD512 in order
to eliminate the noise caused by a hight MCLK rate.
With the new option the SAI1 BCLK is routed to codec MCLK pin.Signed-off-by: Viorel Suman
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com
(cherry picked from commit f9c65f44d0e7da0e5a59dae9434dc0d70cf2039b)
08 Mar, 2018
2 commits
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Currently, the default clock configuration for DCSS configures the pixel
clock to be sourced from VIDEO_PLL2, but this source cannot be used by the
DSI PHY_REF clock.
So, in order to make DCSS working with DSI, we need to have them both
(DCSS and DSI PHY) use the same clock source: VIDEO_PLL1.Signed-off-by: Robert Chiras
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Currently, the default clock configuration for DCSS configures the pixel
clock to be sourced from VIDEO_PLL2, but this source cannot be used by
the DSI PHY_REF clock.
So, in order to make DCSS working with DSI, we need to have them both
(DCSS and DSI PHY) use the same clock source: VIDEO_PLL1.Signed-off-by: Robert Chiras
28 Feb, 2018
1 commit
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This clock is needed by HDR10 so this patch makes DCSS use VIDEO2_PLL2
for the rest of the resolutions as well.Signed-off-by: Laurentiu Palcu
13 Feb, 2018
1 commit
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Currently, on imx8mq evk board, we only support 3200mts and 667mts
frequency setpoints. So the DDR DVFS flow need to be updated accordingly.The dram pll and dram apb clock rate is changed in ATF when doing frequency,
in kernel side, we need to call the clk API to update the clock rate info
in clock tree.Signed-off-by: Bai Ping
Reviewed-by: Anson Huang
(cherry picked from commit ff82ef826f8d2e609e5144c2e98de30bc8ea2547)
11 Feb, 2018
1 commit
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Add the dma int for the the imx pcie ep mode for
the controllers that has the dma capability.Signed-off-by: Richard Zhu
(cherry picked from commit 5e76cceda3375ee760e4ca92ebd1c710fc1128b2)
08 Feb, 2018
1 commit
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The Secure Memory contain 8 pages of 4k byte but the
node was only expressing half this space.Signed-off-by: Franck LENORMAND
07 Feb, 2018
1 commit
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move the pdn gpio to sound card node for ak4458
Signed-off-by: Shengjiu Wang
Reviewed-by: Cosmin Samoila
(cherry picked from commit 54d71caaa6cfb11bfa86170b3ae81b6e07737f8d)
06 Feb, 2018
1 commit
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SAI5_RXDn must be muxed to RX_DATAn. For n = {1, 2, 3}
this mapping was not correctly done so only channels
recorded from data line 0 were seen in .wav capture.Suggested-by: Shengjiu Wang
Signed-off-by: Daniel Baluta
Reviwed-by: Shengjiu Wang
(cherry picked from commit 66f2533b447ae85a95f66cb79f8c7cfc970e3d4e)
01 Feb, 2018
1 commit
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Since M4 will use QSPI and SAI2, disable the relevant nodes in M4
dedicated DTB.Signed-off-by: Ye Li
(cherry picked from commit 835a41dc2cd5f471af3ea6ef0e3d87922295a617)
31 Jan, 2018
2 commits
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According to the Reference manual, the bit 1-4 of PAD setting is reserved.
Signed-off-by: Shengjiu Wang
(cherry picked from commit 908cdceaa0dbf01569f373d63016cdd428e9178b) -
Use a separate dts for tdm mode for ak4458.
Signed-off-by: Cosmin-Gabriel Samoila
Reviewed-by: Shengjiu Wang
(cherry picked from commit de6344dc975a5d7842d0e8138e5abe3557fa09d6)
30 Jan, 2018
1 commit
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As the typec port controller interface(TCPCI) spec requires the i2c clock
at least to be 400K, so here increase it to be 400K to meet timing
requirement.Acked-by: Peter Chen
Signed-off-by: Li Jun
(cherry picked from commit 2857b6e5a605e40a65b3961e15b8949604433de9)
29 Jan, 2018
2 commits
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Use a separate dts for tdm mode for ak5558.
Signed-off-by: Shengjiu Wang
(cherry picked from commit b46544a60ea3a4f64e11485fd5d45981210d93e6) -
This is the requirement for MGS-2914, but will cause cts failure and be reverted later.
New gpu driver 6.2.4.p1.pre2 has fixed the cts failure issue so we disable it again.Date: Jan 26, 2017
Signed-off-by: Yuchou Gan yuchou.gan@nxp.com
26 Jan, 2018
1 commit
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Reparent dpu and hdmi pixel clock from av_pll_bypass.
Signed-off-by: Sandor Yu
Reviewed-by: Robby Cai
(cherry picked from commit 49c2e5dbc62f17f020cb9eda63b9021cdc96c359)
25 Jan, 2018
1 commit
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enable the usb otg for mfgtool download on imx8mq ddr4 arm2 board.
Signed-off-by: Han Xu
24 Jan, 2018
3 commits
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Too many i2c slaves are conencted to imx8qm i2c0 and
imx8qxp lpi2c1. So i2c pad drive strength should be
increased. Otherwise, there will be i2c probe error.Reported-by: Andy Tian
Tested-by: Andy Tian
Signed-off-by: Gao Pan
Acked-by: Fugang Duan -
Update vpu voltage to 1.0v for 600M+ clock
Otherwise, keep 0.9v voltageSigned-off-by: Zhou Peng-B04994
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For most DSD sample rate is mulitply of 44k, so specify PLL2
for DSD usage. for pinmux is different for DSD mode compare with
PCM mode, define a new pinmux group for DSD.Signed-off-by: Shengjiu Wang
Reviewed-by: Viorel Suman
Reviewed-by: Daniel Baluta
23 Jan, 2018
1 commit
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This patch:
- Adds compilation of the secvio driver for all arm64 targets
- Adds the secvio driver to fsl-imx8mq.dtsiSigned-off-by: Franck LENORMAND
22 Jan, 2018
2 commits
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The bit clock for 786KHz, 16bit, 2 channel is 24.576MHz, and the default
divider of SAI is at least 2, so the minimum master clock should be 49MHz.Signed-off-by: Shengjiu Wang
Reviewed-by: Daniel Baluta -
Add emvsim0 device node in register address order
Signed-off-by: Gao Pan
Acked-by: Fugang Duan
19 Jan, 2018
4 commits
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Add enet2 phy regulator for arm2 board to set IO voltage to 1.8v.
Signed-off-by: Fugang Duan
Acked-by: Gao Pan -
Add enet2 phy regulator to fix IO voltage 1.8v for MEK board.
Signed-off-by: Fugang Duan
Acked-by: Gao Pan -
LPI2C1 bus mount many slave devices, the current drive strength is
weak and device probe failed. Then increase the pin drive strength
for LPI2C1 lines.Signed-off-by: Fugang Duan
Acked-by: Gao Pan -
add ecspi device node for imx8mq
Signed-off-by: Gao Pan
Reviewed-by: Andy Duan
18 Jan, 2018
3 commits
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Enable the AK4458, AK5558, and AK4497 with mode 0. For ak4497 use
same SAI interface with AK4458, so move ak4497 device node to
a separate dts.The AK4458 support maximum 16 channels, the AK5558 support maximum 8
channels, AK4497 is for stereo.Signed-off-by: Shengjiu Wang
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add emvsim0 device node for imx8qm-mek to support EMVSIM
Signed-off-by: Gao Pan
Reviewed-by: Andy Duan -
Enable USB3 hardware link power management, so the link can enter
U1 and U2 if there is no data transfer if the deivce can support
them.Signed-off-by: Li Jun
12 Jan, 2018
4 commits
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Delete the dst files specific to dsi/lvds nodes for the 8QXP LPDDR4
platform.Signed-off-by: Robert Chiras
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Delete the dst files specific to dsi/lvds nodes for the 8QM LPDDR4 platform.
Also, update the existing it6263 dts files accordingly.Signed-off-by: Robert Chiras
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Delete the dst files specific to dsi/lvds nodes for the 8QXP MEK platform.
Signed-off-by: Robert Chiras
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Delete the dst files specific to dsi/lvds nodes for the 8QM MEK platform.
Signed-off-by: Robert Chiras