12 Oct, 2019
1 commit
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Driver to communicate with SECO over messaging unit.
Expose a char device to user-space so user can write messages that
will be sent to SECO and read messages received from it.
Data that should be exchanged with SECO through shared memory are
indicated to this driver through ioctl calls.Signed-off-by: Stephane Dion
(cherry picked from commit eb721810fdc309b6a32a7a64c7686eaa6052cdc7)
28 Aug, 2019
1 commit
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Handle the case when powering down a pd with no active slave domains.
Signed-off-by: Ranjani Vaidyanathan
06 Aug, 2019
1 commit
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Fix power state of parent power domains that have no device
associated with them.Current power domain driver does not work well in two cases:
1. A device is controlled by multiple power domains
2. Multiple devices are controlled by a single power domain that
is dependent on another power domain(s).This patch attempts to fix these two issues.
Signed-off-by: Ranjani Vaidyanathan
10 Jul, 2019
1 commit
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This is a porting from 4.14.98
commit ("MLK-18592-1 soc: imx: use vendor hvc to communiate with SCU")
to make dom0 share same MU channel with XEN.Signed-off-by: Peng Fan
Reviewed-by: Jacky Bai
02 Jul, 2019
1 commit
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Add compatible string for i.MX8MN for power domain driver
support.Signed-off-by: Jacky Bai
27 Jun, 2019
2 commits
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Add speed grading fuse check to constrain CPU OPP according
to market segment and speed grading fuse map,Market_Segment[1:0]:
'00' - Consumer 0C to 95C
'01' - Ext. Consumer -20C to 105C
'10' - Industrial -40C to 105C
'11' - Automotive -40C to 125CSPEED_GRADING[5:0]:
SPEED_GRADE[5:4] SPEED_GRADE[3:0] MHz
xx 0000 2300
xx 0001 2200
xx 0010 2100
xx 0011 2000
xx 0100 1900
xx 0101 1800
xx 0110 1700
xx 0111 1600
xx 1000 1500
xx 1001 1400
xx 1010 1300
xx 1011 1200
xx 1100 1100
xx 1101 1000
xx 1110 900
xx 1111 800Signed-off-by: Anson Huang
Reviewed-by: Bai Ping -
This patch adds new SoC i.MX8MN's soc id driver support.
Signed-off-by: Anson Huang
Reviewed-by: Abel Vesa
Reviewed-by: Bai Ping
23 May, 2019
1 commit
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Commit b24e5c5fca92 ("MLK-21078-3 soc: imx: enable RX interrupt
for IPC response") adds IPC RX IRQ support and need to add
IRQF_NO_SUSPEND flag for MU IRQ to make IPC work during system
suspend phase, but with this flag set, IRQD_WAKEUP_ARMED flag will
NOT be set during suspend_device_irq() phase, then when MU IRQ
arrives, it will NOT wake up system from s2idle.To fix this issue, pm_system_wakeup() is called in general MU IRQ
handler to make sure system can be waked up when MU IRQ arrives.Signed-off-by: Anson Huang
Acked-by: Robin Gong
10 May, 2019
1 commit
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We can use the standard DT "reg" property instead of defining our
own "domain-id"Signed-off-by: Leonard Crestez
Acked-by: Jacky Bai
02 May, 2019
1 commit
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This reverts commit f54e714cfc53b9164d1206f9ee49042195532a51.
This patch breaks the suspend and resume functionality in all imx6 boards.
Signed-off-by: Arulpandiyan Vadivel
18 Apr, 2019
30 commits
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This patch updates SCFW API to v1.7, based on below commit:
252281d48647 ("SCF-105: Update wiki.")
Signed-off-by: Anson Huang
Reviewed-by: Bai Ping
(cherry picked from commit d62625563213b516c6238e970f31d07d20bbe19e) -
The power mode operation ONLY checks whether the resource being
powered OFF is a wakeup source, and skip power OFF operation if
it is a wakeup source, but it does NOT consider the power tree
status, if any of its children is a wakeup source, it needs to
be kept powered ON for its children's wakeup capability.For example, on i.MX8QXP, CAN1 shares CAN0's power, if CAN1 is
enabled as wakeup source, CAN0's power needs to be ON even it
is NOT a wakeup source, this patch adds support for such scenario.As it uses recursion, to avoid overhead during runtime power
management, introduce a variable to make sure this logic is ONLY
enabled during suspend/resume.The generic power domain framework for handling device power
according to wakeup status does NOT consider the virtual devices,
e.g., if debug uart is enabled as wakeup source, the device wakeup
capability check for uart device returns false, ONLY the ttydev has
wakeup capability, that will cause resume_needed() return false
and uart device power will be OFF even its child device "ttydev" is
enabeld as wakeup source.Signed-off-by: Anson Huang
Tested-by: Joakim Zhang
Reviewed-by: Bai Ping
(cherry picked from commit 459db9c5f53735f33753a7a60232784b3d09d261) -
This patch fixes coverity issue of "divide by 0".
Signed-off-by: Anson Huang
Reviewed-by: Bai Ping
(cherry picked from commit ed044f6d78156ae603dd732f15c5268d3f545605) -
The 100MTS low bus mode can be only supported by i.MX8MQ Rev2.1 and
future TO. So necessary check is added to identify the chip revision
when doing busfreq mode switch.Signed-off-by: Bai Ping
Reviewed-by: Anson Huang
(cherry picked from commit a906afb17d445b40f6c70fa2a2c3b6707ada0e47) -
add busfreq support on i.MX8MM. when system is running at low bus or
audio bus mode, the dram & bus clock will be reduced to a lower rate:
NOC: 150MHZ, AXI: 24MHz, AXI 20MHZ, DRAM core clock: 25MHz.when system is running at high bus mode, all the bus clock and dram
clock will be restore to the highest one.Signed-off-by: Bai Ping
Reviewed-by: Anson Huang
(cherry picked from commit 4984e653a6e86f7b6e2e6c195be53da8dcb5f8fd) -
Currently, on imx8mq evk board, we only support 3200mts and 667mts
frequency setpoints. So the DDR DVFS flow need to be updated accordingly.The dram pll and dram apb clock rate is changed in ATF when doing frequency,
in kernel side, we need to call the clk API to update the clock rate info
in clock tree.Signed-off-by: Bai Ping
Reviewed-by: Anson Huang
(cherry picked from commit a69c3794f52d826762642cbdcf978a85784f386a) -
A 'return' statement is missed before, So the mutex will be unlocked
twice, in some corner case, one core will unlock the mutex that locked
by anohter core wrongly. Then lead to concurrent access to the DVFS
at the same time.Signed-off-by: Bai Ping
Reviewed-by: Anson Huang
(cherry picked from commit 659615af4d35c7f118b7cf346624d423a3b15797) -
If the system is currently in low bus mode, if the audio device
request the audio bus mode, the NOC, AHB and AXI bus clock rate
will be set wrongly, then bus will run at very low frequency, then
lead to audio playback underrun.Signed-off-by: Bai Ping
Tested-by: Anson Huang
(cherry picked from commit 3a2a988cc02823297d14aa9001f013adbd15f6e8) -
reduce the NOC, main AXI and AHB bus clock frequency to save power when DDR enter low
frequency mode. VDDSOC is ~195mA during video play, and ~180mA in idle.Signed-off-by: Anson Huang
Signed-off-by: Bai Ping
(cherry picked from commit e109b34d30f0b4628a41ca9715eea689cc8c2a56) -
If audio device is the only that access to ddr memory, the DDR
frequency can be reduce to 25MHz to save power. when DDR run in
25MHz frequency, the memory bandwidth is about 66MB/s, it can
meet the performance requirement for audio only case.Signed-off-by: Bai Ping
Reviewed-by: Anson Huang
(cherry picked from commit 7c2389b6dca053ae4b4a56b3588978909769008c) -
Add busfreq driver support on i.MX8MQ. The busfreq driver is
mainly used for dynamic DDR frequency change for power saving
feature. When there is no peripheral or DMA device has direct
access to DDR memory, we can lower the DDR frequency to save
power. Currently, we support frequency setpoint for LPDDR4:(1): 3200mts, the DDRC core clock is sourced from 800MHz
dram_pll, the DDRC apb clock is 200MHz.(2): 400mts, the DDRC core clock is source from sys1_pll_400m,
the DDRC apb clock is is sourced from sys1_pll_40m.(3): 100mts, the DDRC core clock is sourced from sys1_pll_100m,
the DDRC apb clock is sourced from sys1_pll_40m.In our busfreq driver, we have three mode supported:
* high bus mode 3200mts;
* audio bus mode 400mts;
* low bus mode 100mts;The actual DDR frequency is done in ARM trusted firmware by calling
the SMCC SiP service call.Signed-off-by: Bai Ping
Reviewed-by: Anson Huang(cherry picked from commit 60a2002f752404b5fc30b374bc71a3975902eb7a)
Use CONFIG_HAVE_IMX_BUSFREQ instead of just CONFIG_ARCH_FSL_IMX8MQ
Signed-off-by: Leonard Crestez -
For IPC communication, CPU will be busy polling MU RX channel
after sending IPC message if IPC response is needed, such
mechanism wastes too much CPU resource if SCU takes long time
to finish the IPC request, so now enable RX interrupt for IPC
response.Signed-off-by: Anson Huang
Reviewed-by: Bai Ping -
Previously, RPMSG uses M4 domain's MU which is inside
intmux irq domain, and RPMSG irq has IRQF_EARLY_RESUME
set, so intmux needs to be powered up at syscore phase
before irqchip resume. Now RPMSG switches to use LSIO's
MU which is inside GIC irq domain, so no need to have
early power on operation for intmux, remove it.Signed-off-by: Anson Huang
Reviewed-by: Bai Ping -
We are currently using SC_R_LAST as a marker for imx8 power domain tree
nodes without a resource attached. This value is compiled into dtb as
part of the linux build and used by uboot.The SC_R_LAST constant changes frequently as SCFW resources are added
(by design) and every time we need to update linux and uboot headers
together or boot can fail.Fix this by replacing SC_R_LAST usage with a new constant SC_R_NONE
defined to be 0xFFF0.Signed-off-by: Leonard Crestez
Reviewed-by: Peng Fan
(cherry picked from commit f573dbd5ce119740ad30b663e3599cb75e6f67ed) -
Copy from rel_imx_4.14.98_2.0.0_ga_rc1
Signed-off-by: Bai Ping
Signed-off-by: Anson Huang
Signed-off-by: Leonard Crestez -
Copy from rel_imx_4.14.98_2.0.0_ga_rc1
Signed-off-by: Anson Huang
Signed-off-by: Peng Fan
Signed-off-by: Leonard Crestez -
Copy from rel_imx_4.14.98_2.0.0_ga_rc1
Signed-off-by: Anson Huang
Signed-off-by: Dong Aisheng
Signed-off-by: Ranjani Vaidyanathan
Signed-off-by: Leonard Crestez -
This is enabled via CONFIG_HAVE_IMX_SC
Copy from rel_imx_4.14.98_2.0.0_ga_rc1
Signed-off-by: Anson Huang
Signed-off-by: Leonard Crestez -
Uses same layout as imx_4.14.y
Signed-off-by: Anson Huang
Signed-off-by: Leonard Crestez -
This patch fixes coverity issue of "divide by 0".
Signed-off-by: Anson Huang
Reviewed-by: Bai Ping
Signed-off-by: Arulpandiyan Vadivel -
MU is shared between rpmsg driver and the multi-core
power management on i.MX6SX and i.MX7D, the RIE3 is
enabled by MU driver, but when rpmsg is probed, it
will call MU_Init and RIE3 will be clear and cause
multi-core power management never work, so do NOT
clear RIEn during MU initialization for i.MX6SX and
i.MX7D.Signed-off-by: Anson Huang
Reviewed-by: Peng Fan
Signed-off-by: Arulpandiyan Vadivel -
Generally read mu registers will take about 225ns.
Overall scu_clk_enable function takes about 8000ns to 150000ns.
Although read version register just take 3% time,
it is not necessary to read version register every time.Signed-off-by: Frank Li
Signed-off-by: Vipul Kumar -
- Add the timeout mu msg send api.
- Use the timeout mu send message function to do the
notification when multi-vdev is enabled on one channel.Signed-off-by: Richard Zhu
Signed-off-by: Vipul Kumar -
- add the MU version1.0 (introduced by 7ulp)
support.
- add the MU_SetFn and MU_ReadStatus APIs.
- fix one mispell bug when enable the RX INTs.
Otherwise, the RX INTs wouldn't be configured
correctly.Signed-off-by: Richard Zhu
Signed-off-by: Vipul Kumar -
Message can be transferred between remote
device and iMX7ULP M4.
Then the message can be transferred between A7
and M4 by rpmsg channel.
demo howto:
- insmode the imx_rpmsg_tty.ko module after
login A7/Linux.
- Receive messages. Used the following command
to dump out the msg from the virtual tty.
./unit_tests/mxc_mcc_tty_test.out /dev/ttyRPMSG 115200 R 100 1000 &
- Send: use the following command to send the
message to M4.
echo /dev/ttyRPMSGSigned-off-by: Richard Zhu
Signed-off-by: Vipul Kumar -
Add i.MX8 SCFW API support.
Based on below commit:
(fcd0efb5f2550712bd7d27f1279e51f7f687f71d)
Fix MX8 MU driver to follow Linux coding conventions.
Remove unused functions.Signed-off-by: Anson Huang
Signed-off-by: Ranjani VaidyanathanAdded to drivers/soc/imx instead of drivers/soc/imx8
Skipped imx8 imx_rpmsg codeSigned-off-by: Leonard Crestez
(Vipul: Fixed merge conflicts and ignore imx8 changes)
TODO: checkpatch warnings
Signed-off-by: Vipul Kumar -
The vendor tree does imx7 PGC management through regulator notifiers
while upstream implemented the same features using power domains. These
two drivers have entirely different interfaces with higher-level IP
blocks.Resolve this conflict by moving the old code to drivers/soc and
supporting both power-domain and regulator interfaces. This effectively
merges the two drivers and is similar to how imx6sx implements both
power domains and a regulator notifier for pcie specifically.Supporting both interfaces allows consumes to switch one-by-one, for
example by having PCI work with a power-domains reference while usb hsic
still uses the regulator enable/disable interface.Signed-off-by: Leonard Crestez
[Arul: Fix merge conflicts]
Signed-off-by: Arulpandiyan Vadivel -
This was introduced while porting patches from imx_4.9.y. In the 4.9
branch there are specific power_on and power_off functions for PU but in
upstream this code was refactored to make the code generic for each PGC
block.Fixes: ce181a6440dc ("MLK-13479-1: ARM: imx: gpc: delay 2us instead of sw+sw2iso delay")
While we're at it remove GPU_VPU_{PUP,PND}_REQ because they're not used.
Upstream forgot to delete these bits while refactoring.Signed-off-by: Leonard Crestez
Acked-by: Richard Zhu
Signed-off-by: Arulpandiyan Vadivel -
With new bindings the PU regulator is fetched much later, after
imx_gpc_probe is complete. So hack the imx_pgc_power_domain_probe
function to check for fsl,ldo-bypass at this point.This issue only actually affects imx6qp because on other SOCs with a
vddpu regulator is it disabled on boot and settings are copied from
vddsoc on first enable, see commit 64dd7300a334 ("MLK-11407-3:
regulator: anatop: force vddpu to use same voltage level as vddsoc")On imx6qp however disabling the PU regulator is not allowed because of
hardware errata.Fixes: 94e8d6daea9a ("MLK-11407-1 soc: imx: gpc: enable PU bypass")
Signed-off-by: Leonard Crestez
Reviewed-by: Anson Huang
Signed-off-by: Arulpandiyan Vadivel -
(sw + sw2iso) delay after raise power up request to pgc is still not
enough stable, so we have to delay 2us to make sure pgc power up
successfully as v3.14. Align the power off flow with v3.14 too.Signed-off-by: Robin Gong
Make ipg_clk global because rate is being fetched dynamically with both
old and new bindings.Signed-off-by: Leonard Crestez
Signed-off-by: Arulpandiyan Vadivel
