23 Feb, 2017
40 commits
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1. Per design requirement, EXSC for PCIe will need clock to recover RDC
setting on resume when M/F mix is off, so we need to enable PCIe
LPCG before entering DSM.2. As M4 clock is disabled in low power mode, after exit from DSM, A7
needs to restore TCM for M4, but without M4 clock, this operation
never success, so we enable A7 wakeup sources for M4 as well during
DSM, after exit DSM, M4's original wakeup sources will be restored.Signed-off-by: Anson Huang
(cherry picked from commit 847db79957d25545c762670eb1bc003f34cb2592)
Signed-off-by: Teo Hall -
On i.MX7D, only when M4 enters STOP mode, system is able to enter DSM
mode where M4 power will be gated off. This is done by checking
a variable which records M4's power mode. However, when system
resume from DSM, M4 is re-enabled to RUN mode by A7, but the variable
is NOT updated accordingly, so next time system suspend, even
M4 is NOT in STOP mode, system can enter DSM mode, which is
unexpected and would cause bus-freq use count mismatch.Fix this issue by reset M4 power mode to RUN mode when resume
from DSM.Signed-off-by: Anson Huang
(cherry picked from commit d22127a8f395edaf719a5bf4874cf22c5bdc8661)
Signed-off-by: Teo Hall -
For DSM mode, M4 TCM context is lost and A7 will restore them
after resume and write TCM entry to M4 and re-kick it. It
assumes M4 is running on TCM, but M4 also has case of running
image on DDR, OCRAMS first 2 words stores the stack and pc
address for M4, to support M4 running on both TCM and DDR
case, we can just leave the OCRAMS first 3 words unchanged
during DSM, the third words is also reserved for M4, as OCRAMS
can keep its context during DSM.This patch leaves OCRAMS first 3 words unchanged and remove
the re-program of TCM entry after exit from DSM, thus it can
support DSM mode for M4 running on TCM/DDR/OCRAM.Signed-off-by: Anson Huang
(cherry picked from commit b8c47389d16dacf3a78c0f92e6737d09811c45a9)
Signed-off-by: Teo Hall -
Save M4 tcm in ddr. Copy memory after exit from DSM.
Also hold M4 in reset when entering DSM.Signed-off-by: Teo Hall
(cherry picked from commit 011ed0ab784eb566b68ebacea57ae3a6857b48ff) -
add tcm to dtsi for saving FreeRTOS image
Signed-off-by: Teo Hall
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change the slots to persistent to be congruent with
M4 image. Also change so that slots do read/modify/write
so that M4 settings are not overwritten.Signed-off-by: Teo Hall
(cherry picked from commit eae33480b615c1586248a761ef3c6bcd9e0c59af)Conflicts:
arch/arm/mach-imx/gpcv2.c -
add LPM messages for:
-M4 reporting state
-M4 Request/Release High Bus Freq
-A7 tell M4 it is readySigned-off-by: Teo Hall
(cherry picked from commit 52234ae38e6e4f2b3452d807dd1c1e199be6350c)Conflicts:
arch/arm/mach-imx/common.h
arch/arm/mach-imx/mu.c -
offset high_bus_count+1 when m4 is enabled
Signed-off-by: Teo Hall
(cherry picked from commit 58983b6522c324affdbbeaa5b7b192a673c615a7) -
Add mlb support for imx6sx-sabreauto platform.
Signed-off-by: Gao Pan
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Moving fsl,tuning-step property into SoC.dtsi due to it's mainly SoC
dependant. User could also overwrite it in board.dts for special board
requirment.Signed-off-by: Dong Aisheng
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MX7D uSDHC has a bit long delay line in SoC internally, pre-set a safe
tuning start point to skip first 20 meaningless cells tuning.Signed-off-by: Dong Aisheng
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Detailed reproduce steps:
1. boot-up to Linux command prompt .
2. Plug SD3.0 UHS-I SD Card into SD3 Connector (make sure SD Card running
at SD3.0 DDR50/1.8V).
2. write data to SD3 using "dd" command (SD3_CLK running at 1.8V/50MHz).
3. capture the SD3_CLK, SD3_DATA, SD3_CMD waveforms during data write using
FET probe (>=1GHz)
4. CLK waveforms like triangular wave are observed.HW team found that the pad setting of the SD3_CLK, SD3_DATA, SD3_CMD signal pins are
not optimized. In existing BSP, when running at SD3.0/DDR50/1.8V, SPEED/DSE/SRE
= 01/011/1 is used. They propose change it to -
SD3_CLK: SPEED/DSE/SRE = 01/110/1.
SD3_DATA/SD3_CMD: SPEED/DSE/SRE = 01/101/1.SDHC high speed cards also had such issue(refer to MLK-9500).
We only changed the default state (
(cherry picked from commit 69d4195c741050e0bc78d3005f8ff4f51990d1ae)Conflicts:
arch/arm/boot/dts/imx6sx-sdb.dts -
CAN devices are allocated to run on M4.
So do not touch CAN pads setting if M4 is enabled.Signed-off-by: Dong Aisheng
(cherry picked from commit 9d2605e51b9ba83382c5da3a838656c9910d75a1) -
Since i.MX6SX, if USB vbus wake up is enabled, weak 2P5
needs to be on even if the DRAM is LPDDR2, previously, we need
to set stop_mode_config to keep 2P5 on, so enter DSM,
if USB vbus wakeup is enabled, we need to keep weak 2P5 on.Signed-off-by: Anson Huang
(cherry picked from commit 1ca4dffee79055ea95c59e27bab50bc5080310f5)
Signed-off-by: Peter Chen -
The GPC setting should be modified using the read-modify-update flow.
Signed-off-by: Bai Ping
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Set tx-d-cal to be 0x5 to improve usb signal quality.
Signed-off-by: Li Jun
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Set tx-d-cal to be 0x5 to improve usb signal quality.
Signed-off-by: Li Jun
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Set tx-d-cal to be 0x5 to improve usb signal quality for all imx6qdl
sabresd boards.Signed-off-by: Li Jun
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- Delete regulator-always-on for 3p0 since it needs to enable/disable
on the fly.
- Add "anatop-enable-bit" property as the offset of enable bit for
3p0, 1p1, and 2p5.
- USB PHY refers "reg_3p0" phandle at its node.Signed-off-by: Peter Chen
(cherry picked from commit c2c2cbc46fda3e8ea798d270a3410f351af9d1ca) -
When SMP is deselected, ARM_ARCH_TIMER is still enabled while
broadcast time is disabled, so when system enters WAIT mode,
ARM platform's clock will be disabled, then system tick timer
will stop and cause system stay at WAIT mode and timer event
will NOT come as expected.To fix this issue, we do runtime check in kernel boot up,
if SMP is NOT enabled, ARM_ARCH_TIMER will be disabled and
using GPT timer always.we have to put this check in early stage before common
arm_arch_timer driver probed.Signed-off-by: Anson Huang
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i.MX7D TO1.1 updates the DDR script, ddr frequency scale flow
should be updated accordingly.Add runtime revision check to support both TO1.0 and TO1.1.
Signed-off-by: Anson Huang
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i.MX7D TO1.1 adds some DDR PHY register settings to fix the CKE
timing issue, when fast MIX off in DSM, need to restore them
to make sure the DDR PHY setting is correct.Signed-off-by: Anson Huang
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Design team recommend to put SCU/C0/C1 in same power up slot
to avoid reset timing issue of debug mode, adjust the power
up slot and timing per their requirement.Signed-off-by: Anson Huang
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Add imx6q/dl/qp sabresd, imx6sx sabreauto magic packet support.
Signed-off-by: Fugang Duan
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Originally we put all the definition of both imx7d normal pins and
lpsr pins in imx7d-pinfunc.h which may lead to a easy failure of
user by wrongly put the normal pins of &iomuxc under &iomuxc_lpsr
node due to user has no idea about the difference, then pinctrl
driver will take the wrong value to set which may potentially break
other devices to work.We have met this issue several times and it's hard to debug when it
happens.This patch separates the lpsr pins into a dedicated head file
to give user a reminder to put lpsr pins group under the correct
pinctrl device node.Signed-off-by: Dong Aisheng
(cherry picked from commit c524454c24fd9e5e329351dd154cbd24d47d0e0e) -
pinmux settings using GPIO1_IO0[0-7] should use iomuxc_lpsr,
but not iomuxc. If use iomuxc, you will set wrong register
and may impact other functions.Without this patch, SAI3_MCLK use GPIO1_IO03 pinmux and impacts
QSPI function.Signed-off-by: Peng Fan
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Add sensor node in 6sx-ard dts. The sensors are mma8451,
mag3110 and isl29023.Signed-off-by: Gao Pan
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ARM does NOT execute one instruction every cycle, the bus bandwidth,
cache status etc. would impacts the instruction execution time, so we
can NOT just calculate the delay time by ARM frequency, this patch
adjusts loop number to get a ~20us delay, measured via GPIO pin.Signed-off-by: Anson Huang
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Per design team's recommendation, for i.MX7D TO1.1
LPSR mode, as IOMUXC will lost power, so it needs to
use TO1.0's flow to avoid CKE toggle during retention,
but it has a limitation of POR reset fail during LPSR.Signed-off-by: Anson Huang
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On v4.1, use syscon-poweroff driver instead of poweroff interface in
rtc-snvs driver.Signed-off-by: Robin Gong
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enable snvs-poweroff driver on imx6sx(except sabreauto board),imx6ul and
imx7d all boards.Signed-off-by: Robin Gong
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Change GPIO pad setting to control EPDC/ENET signals on REV B board from 0x59
to default one 0x14 in order to remove stripe when do EPDC unit test.Signed-off-by: Robby Cai
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Disable can2 is not enough, since the reg_can2_3v3 will be turned off by
the regulator framwork and that will impact can2 in m4 side even if can2
driver disabled in A7 side.Signed-off-by: Robin Gong
(cherry picked from commit f1bd999df30c6e88c1a967856304086aa72f2db0) -
This patch cherry-pick from the below commit, but make little change:
align i.mx6dl with i.mx6q, since TKT238285 should be exit on other chips
although it can't reproduced by SPI-NOR, now there is official workaround
for this bug(a619a00e11a67b00805b9148f004a3c94d54f863). So this patch just
enable dma support on i.mx6sl and i.mx6sx.*****************
There is one BUG(TKT238285) in ecspi module in DMA mode,but
it only found on i.mx6dl now, so enable dma support on all
i.mx6 chips except i.mx6dlSigned-off-by: Robin Gong
(cherry picked from commit fa9ef1796819aadbb1ea184613d4fdd3de1b46c6)
(cherry picked from commit cfedad0e853fbcd5e57591b559734d54cdb782c8) -
EPDC board has touch screen, this patch add touch support on imx7d-sdb TO1.1
board, due to the touch pin conflict with UART5 and GPMI, so disable UART5 in
imx7d-sdb-epdc.dtsi. For GPMI, it default disabled in imx7d-sdb.dts, so do not
impact touch.Signed-off-by: Haibo Chen
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SCU PGC register is different from others, it contains
other timing settings, so we can NOT just program 0/1
to disable/enable SCU power gating, but need to only
program bit 0, correct it for all modules' PGC settings.Signed-off-by: Anson Huang
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- Update i.MX6ul iomux haeders to b151130 version.
- Merge the origin two pinfunc:
MX6UL_PAD_BOOT_MODE0__GPIO5_IO10
MX6UL_PAD_BOOT_MODE1__GPIO5_IO11Signed-off-by: Fugang Duan
(cherry picked and merged from commit: f9bab6534f9f) -
Fixed no /proc/config.gz is found in /proc.
Signed-off-by: Frank Li
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enable debugfs in mfg_defconfig for mfgtool to read bch layout setting
from debugfs.Signed-off-by: Han Xu
(cherry picked from commit a4a31e73897b51b73b1be994d36759584407914f) -
We move WDOG_B pinctrl setting from pinctrl_hog to wdog driver, so need to
remove the original setting in pinctl_hog device node, otherwise the below
warning message will be caught:[ 1.284161] imx6ul-pinctrl 20e0000.iomuxc: pin MX6UL_PAD_LCD_RESET already requested by 20e0000.iomuxc; cannot claim for 20bc000.wdog
[ 1.294990] imx6ul-pinctrl 20e0000.iomuxc: pin-69 (20bc000.wdog) status -22
[ 1.300689] imx6ul-pinctrl 20e0000.iomuxc: could not request pin 69 (MX6UL_PAD_LCD_RESET) from group wdoggrp on device 20e0000.iomuxc
[ 1.311550] imx2-wdt 20bc000.wdog: Error applying setting, reverse things backSigned-off-by: Robin Gong