12 Oct, 2019
1 commit
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Documentation of device-tree entry describing messaging
unit (MU) used to communicate with SECO core on i.MX8.Signed-off-by: Stephane Dion
(cherry picked from commit 238c7e4dab3b500c61b7def62dcd940b9c103658)
16 Aug, 2019
1 commit
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The rpmsg i2s audio is supported with codec wm8524 in imx8mn
Signed-off-by: Shengjiu Wang
(cherry picked from commit 68ad8218321cec6006acdb3df846da8bc6994792)
06 Aug, 2019
1 commit
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imx8mm has 2 chipidea usb2 cores, add its compatible.
Signed-off-by: Li Jun
24 Jul, 2019
1 commit
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Add power domains for each dma channel so that edma channel could
know the power state of every dma channel anytime and clear easily
unexpected interrupt which triggered before the last partition reset.Signed-off-by: Robin Gong
Reviewed-by: S.j. Wang
(cherry picked from commit 0b6da46b7bdb2284e24757d48466268b9feb5b7c)
19 Jul, 2019
1 commit
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EASRC (Enhanced ASRC) is a new IP module found on i.MX8 MN. It is
different from old ASRC module.Signed-off-by: Shengjiu Wang
Reviewed-by: Daniel Baluta
Reviewed-by: Viorel Suman
09 Jul, 2019
1 commit
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This is an adapter card made for the 4.3", 800x480, LCD panel Seiko
43WVFIG. The LCD panel is a 24bit DPI bus, while the adapter card has
two ports: 18-bit and 24-bit data input. For the 18-bit data input, the
adapter card is demuxing some of the data lines, in order to feed all of
the 24 lines needed by the LCD.
This driver handles both this use-cases.Signed-off-by: Robert Chiras
02 Jul, 2019
1 commit
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Add a compatible string which includes 'imx8mn' for both
LCDIF and DSIM drivers.Signed-off-by: Fancy Fang
27 Jun, 2019
1 commit
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This is an reset driver to implement a reset controller
device DISPMIX on IMX8MM and IMX8MN platforms. Dispmix
reset is used to reset or enable related buses and clks
for the submodules in DISPMIX.All the dispmix resets are divided into three subgroups:
sft_rstn, clk_en and mipi_rst, and each of them contains
several reset lines to control several different modules
on and off in DISPMIX which doesn't require the standard
reset flow, but only line assert and deassert operations.Signed-off-by: Fancy Fang
21 Jun, 2019
3 commits
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Add documentation for new dts property 'clock-drop-level' in order to allow
the user to determine how much the crtc_clock (the real pixel clock) should
be dropped below the actual DSI clock.Signed-off-by: Robert Chiras
Reviewed-by: Laurentiu Palcu -
Revert this patch in order to re-implement this logic.
This reverts commit 01ba61aee0e2487e14c11c24a0eb3787fd3c990c.Signed-off-by: Robert Chiras
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Add imx8qxp compatible string for i.MX8 SoCs.
Signed-off-by: Clark Wang
Acked-by: Fugang Duan
07 Jun, 2019
1 commit
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Since L4.15, community involve the commit 105819c8a545 ("mmc: core: use mrq->sbc
when sending CMD23 for RPMB"), let the usdhc to decide whether to use ACMD23 for
RPMB. This CMD23 for RPMB need to set the bit 31 to its argument, if not, the
RPMB write operation will return general fail.According to the sdhci logic, SDMA mode will disable the ACMD23, and only in
ADMA mode, it will chose to use ACMD23 if the host support. But according to
debug, and confirm with IC, the imx6qpdl/imx6sx/imx6sl/imx7d do not support
the ACMD23 feature completely. These SoCs only use the 16 bit block count of
the register 0x4 (BLOCK_ATT) as the CMD23's argument in ACMD23 mode, which
means it will ignore the upper 16 bit of the CMD23's argument. This will block
the reliable write operation in RPMB, because RPMB reliable write need to set
the bit31 of the CMD23's argument. This is the hardware limitation. Due to
imx6sl use SDMA, so for imx6qpdl/imx6sx/imx7d, it need to broke the ACMD23 for
eMMC, SD card do not has this limitation, because SD card do not support reliable
write.For imx6ul/imx6ull/imx6sll/imx7ulp/imx8, it support the ACMD23 completely, it
change to use the 0x0 register (DS_ADDR) to put the CMD23's argument in ADMA mode.This patch handle 'auto-cmd23-broken' from devicetree.
Signed-off-by: Haibo Chen
24 May, 2019
1 commit
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Refer to the 32bits DMA limitation, specify the dma ranges memory region
of iMX8 PCIe in the 32bits address space.Signed-off-by: Richard Zhu
18 Apr, 2019
27 commits
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This patch is to add CAN wakeup function on MX8 platforms and update the
binding file fsl-flexcan.txt.For MX8, the function "flexcan_irq()" should not call "flexcan_exit_stop_mode()"
due to firmware(SCU) cannot make SC IPC calls from an interrupt context.
If not exit stop mode in ISR, it will continuously enter wakeup ISR for the reason
that system will respond IRQ before call CAN system resume.
To fix the issue, we can exit stop mode during noirq resume stage.For wakeup case, it should not set pinctrl to sleep state by
pinctrl_pm_select_sleep_state.Signed-off-by: Joakim Zhang
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Add "fsl, imx8mm-usdhc" for imx8mm
Signed-off-by: Haibo Chen
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This adds the binding for the USB3 PHY found on the i.MX8M SoC.
Signed-off-by: Lucas Stach
Reviewed-by: Rob Herring
Signed-off-by: Kishon Vijay Abraham I
(cherry picked from commit 3c2ce40b2fbb52b5e861f8664f5422d39f11b39e) -
Add new compatible string for i.MX6ULL SOC.
Signed-off-by: Vipul Kumar
(cherry picked from commit 33b8d7a98f51b2084aaf419d6407f2a7d33cb18f) -
1. imx_4.14.y commit ("6c68d27892c4 MLK-18082: boot: dtsi: Align DTSI")
changes in Documentation/devicetree/bindings/crypto/fsl-sec4.txt were
omitted, add them now.2. Some commits (see Fixes tags) are incomplete / merge conflict
resolutions are incorrect.Fixes: 0cab3173f44a ("MLK-18082: ARM: dts: imx: Change size of caam-sm to correct size")
Fixes: 9c5e81b8410b ("MLK-9710-18 snvs - make SECVIO module device tree correct")
Reviewed-by: Franck LENORMAND
Reviewed-by: Iuliana Prodan
Signed-off-by: Horia Geantă -
Add ROHM BD71837 / BD71847 specific device tree bindings for
controlling the PMIC shutdown/reset states and voltages for
different HW states. The PMIC was designed to be used with NXP
i.MX8 SoC and it supports SNVS low power state which seems to
be typical for NXP i.MX SoCs. However, when SNVS is used we must
not allow SW to control enabling/disabling those regulators which
are crucial for system to boot as there is a HW limitation which
causes SW controlled regulators to be kept shut down after SNVS
reset.Allow setting the SNVS to be used as reset target state and allow
marking those regulators which are critical for boot.Signed-off-by: Matti Vaittinen
Tested-by: Angus Ainslie
Reviewed-by: Angus Ainslie
Signed-off-by: Mark Brown
(cherry picked from commit f43d1b388f9be4aa47ed42c33659243a675c5c76) -
Add ROHM BD71847 Power Management IC MFD binding information to
device-tree binding documents.Signed-off-by: Matti Vaittinen
Reviewed-by: Rob Herring
Acked-by: Lee Jones
Signed-off-by: Mark Brown
(cherry picked from commit 01e17e5d8004f53044c6c9062e04ca118c420512) -
Add ROHM BD71847 Power Management IC regulator binding information to
device-tree binding documents.Signed-off-by: Matti Vaittinen
Reviewed-by: Rob Herring
Signed-off-by: Mark Brown
(cherry picked from commit 12fc309a956b82e75db2a19fd36074266bff9413) -
In order to support 44kHz and 48kHz sample rate together, we need to
reconfigure the parent clock of mclk.Signed-off-by: Shengjiu Wang
(cherry picked from commit 3bc7e6bcca6613e43b7dab98b5a16d2c8097d29e) -
On imx8qm mek, the cs42888 is connected with i2c in cm41 domain,
but wm8960 is connected with i2c1, which is not in m4 domain.
So we only need to eable rpmsg for cs42888.Signed-off-by: Shengjiu Wang
(cherry picked from commit 9d2368aef40e4d107e4deee1a2c7e191c1afe644)
(cherry picked from commit dd108f1dd88feb55cd9a31f135ae6481b8e6774b) -
Remove "model" attribute.
Signed-off-by: Viorel Suman
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Add the DT binding documentation for NXP Audio Mixer
CPU DAI driver.Signed-off-by: Viorel Suman
Signed-off-by: Mark Brown
(cherry picked from commit d0d9071b724123ebde89bdf6b52b86c3289abe85) -
This reverts commit 1a6856077fd7dfdbbd226b84d02d3edbc5fc6948.
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Add virtual i2c driver to send SRTM i2c messages to M4.
Each virtual I2C bus has a specal bus id, which is abstracted by M4.
Each SRTM message include a bus id for the bus which the device is on.Virtual i2c rpmsg bus will bind rpbus nodes with compatible string
"fsl,i2c-rpbus". And "rpmsg-i2c-channel" will probe only one rpmsg
channel for all rpbuses.This virtual i2c driver depends on CONFIG_I2C and CONFIG_RPMSG.
Signed-off-by: Clark Wang
(cherry picked from commit 9feeac93a7d91ce67537a8a6c67e624eb7986a01) -
A low pulse whose width is at least 40ms on pin SYSRSTN
may reset the bridge, according to the chip maker.
This patch adds gpio reset support for the bridge.Signed-off-by: Liu Ying
(cherry picked from commit 2e120abcef4da663bc63f42a017697c937205598) -
This patch adds IT6263 video support.
Signed-off-by: Liu Ying
(cherry picked from commit bf1acefa6ef424caa4c0b37ae022d25c1028984f) -
i.MX8qxp uses two LDB(one primary, one auxiliary) to support dual
channel mode. This patch adds DT property descriptions for those
properties needed by this case.Signed-off-by: Liu Ying
(cherry picked from commit d07d63c135b18000cee1d14be2e257d2f791e574) -
This patch adds i.MX8qxp LDB support.
Logics are added to make i.MX8qxp LDB cope with Mixel LVDS combo PHY.
Also, logics are added to handle pixel link quirks for i.MX8qxp LDB.Signed-off-by: Liu Ying
(cherry picked from commit 086248a0dc2a4291577c3b3eb58fb0b17669d037) -
This patch adds i.MX8qm LDB support.
Logics are added to make i.MX8qm LDB cope with Mixel LVDS PHY.
Also, logics are added to handle pixel link padding quirks for i.MX8qm LDB.Signed-off-by: Liu Ying
(cherry picked from commit d8e089c7a45ce66c34db8682435bf31ad7be148a) -
Fast-forward dpu common driver from imx_4.14.y.
Signed-off-by: Liu Ying
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Fast-forward imx8_pc driver from imx_4.14.y.
Signed-off-by: Liu Ying
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Fast-forward imx8_dprc driver from imx_4.14.y.
Signed-off-by: Liu Ying
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Fast-forward imx8_prg driver from imx_4.14.y.
Signed-off-by: Liu Ying
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specify the spdif in imx8mm for the ipg clock is higher that
it can support 192kHzSigned-off-by: Shengjiu Wang
Reviewed-by: Viorel Suman
(cherry picked from commit bfae9cfe49f5176ad816bf98d076ba7b0fc95593) -
This patch adds base suport for i.MX8M's Display Controller
subsystem(DCSS). It has built-in DPR, Scaler and HDR10 modules. Also, it
features a video Decompression and Tile to Raster Conversion (DTRC) unit,
as well as a graphics pixel decompression infrastracture (DEC400D).Signed-off-by: Laurentiu Palcu
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Add a new property 'pref-rate' support which can be used to
assign a different clock frequency for the DPHY PLL reference
clock in the dtb file. And if this property does not exist,
the default clock frequency for the reference clock will be
used. And according to the spec, the DPHY PLL reference clk
frequency should be in [6MHz, 300MHz] range.Signed-off-by: Fancy Fang
(cherry picked from commit a9fafe8108505f8a1580af898ff5fa9c26d03680) -
Add a new property 'video-mode' binding for panel rm67191
which is used to specify a video data transfer mode.Signed-off-by: Fancy Fang
(cherry picked from commit 9dba8643d7b9c73a2b20ef517c79bb799f5ade3d)
(cherry picked from commit 6a427c8e9c4ae06cb84a7d8c70b7a95cf92b4206)
