15 Mar, 2019
1 commit
-
We need to set parent clock for some audio clock in dts,
when the system enter suspend, the whole audio subsystem
may be power off, the parent setting should be lost, so
we need to set CLK_SET_PARENT_NOCACHE flag in imx_clk_mux_scu,
to let the operation of reset parent clock in
drivers/soc/imx/pm-domains.c take effect.This issue only occurs on imx8qm, not on imx8qxp, for on imx8qxp
the ADMA subsystem don't enter power off, there is other
device in power on state in suspend.Signed-off-by: Shengjiu Wang
(cherry picked from commit 5e8b48b90effa1aa2b9fbbd8919b131f6ad86946)
05 Mar, 2019
2 commits
-
The DSI PHY_REF clock for the second DSI instance was missing from the
clock driver, so add it now.Signed-off-by: Robert Chiras
Reviewed-by: Laurentiu Palcu -
Add the missing clocks for the DSI PHY_REF:
IMX8QM_MIPI0_DSI_PHY_CLK and IMX8QM_MIPI1_DSI_PHY_CLK.Signed-off-by: Robert Chiras
Reviewed-by: Laurentiu Palcu
20 Feb, 2019
1 commit
-
Audio PLL is a frac pll, the config for this PLL should follow
below limitation:
Fout = ((m + k / 65536) * FIN) / (p * 2^s),
Fvco = ((m + k / 65536) * FIN) / p
Fref = FIN / pa). 6MHz
Reviewed-by: Anson Huang
(cherry picked from commit 9a774f3e8bfce2fcd2472b8656f84a452276a7a8)
12 Feb, 2019
36 commits
-
For the sim_hsio clock, it is used by the HSIO mix.
previously, we keep this clock gate always-on, and
don't expose it into linux. In order to save power,
we need to runtime enable/disable this clock.Signed-off-by: Jacky Bai
-
This patch fixes below coverity issues:
CID 17326/17327: Unintentional integer overflow (OVERFLOW_BEFORE_WIDEN)
overflow_before_widen: Potentially overflowing expression div *
parent_rate with type unsigned long (32 bits, unsigned) is evaluated
using 32-bit arithmetic, and then used in a context that expects an
expression of type u64 (64 bits, unsigned).Signed-off-by: Anson Huang
Reviewed-by: Bai Ping -
Fix an obvious typo when clock IMX8QM_DC1_PLL0_DIV is registered:
clks[IMX8QM_DC1_PLL1_DIV] -> clks[IMX8QM_DC1_PLL0_DIV]Only MIPI DSI2 is likely to be impacted by DC1 display port0.
Tested 1920x1080p@60 and 1920x1080p@50 video modes via ADV7535(MIPI DSI
to HDMI transmitter) driven by MIPI DSI2. They are okay.Fixes: b290273aa8a7 ("MLK-13911-10 clk: imx: imx8qm: add clk driver")
Reported-by: Jason Liu
Cc: Anson Huang
Cc: Robert Chiras
Signed-off-by: Liu Ying -
There are some problems in the 8QXP MIPI SS clock tree relating with LPCG:
1. i2c0 and i2c1 uses wrong registers and bits. i2c0 lpcg acutally is at
offset 0x10 and i2c1 is at 0x14, ipg_clk and ipg_clk_s at bit 16 and
i2c_clk is bit 0.
2. pwm uses wrong bit for 32k_clk, should be bit 4.
3. gpio uses wrong bit for ipg_clk, should be bit 16.Also since the ipg_clk and ipg_clk_s share same LPCG offset and bits, we only
need to register one clock. So remove ipg_clk_s from clock tree.Signed-off-by: Ye Li
Reviewed-by: Ranjani Vaidyanathan -
The power domain seems to be wrong for this clock and this can cause
xrdc enforcement errors.It is not easy to reproduce on imx_4.14.y but can be verified using SCFW
monitor.Signed-off-by: Leonard Crestez
Acked-by: Nitin Garg -
Now that there is a generic SCCG clock added, it can also
be used by the DCSS. The HDMI_PHY_27M_CLK ref sel is hardcoded as parent
to VIDEO_PLL2 in dts.Signed-off-by: Abel Vesa
Reviewed-by: Laurentiu Palcu -
Make the entire combination of plls to be one single clock. The parents used
for bypasses are specified each as an index in the parents list.
The determine_rate does a lookup throughout all the possible combinations
for all the divs and returns the best possible 'setup' which in turn is used
by set_rate later to set up all the divs and bypasses.Signed-off-by: Abel Vesa
-
Keep the DRAM PLL always on by default on i.MX8MQ.
Signed-off-by: Bai Ping
Reviewed-by: Anson Huang -
No way of knowing when any of the uart clocks is currently
in use by m4 so just skip the gating for all of them.Signed-off-by: Abel Vesa
Reviewed-by: Leonard Crestez -
Ignoring the gating of composite clocks if m4 is active is necessary
since any of those clocks can be in use by m4 at any given time.Signed-off-by: Abel Vesa
Reviewed-by: Leonard Crestez -
This reverts commit 322503a15740bd9383bb4ed452e5dd5a40598170.
The driver for clk-pllv3 has moved from arch/arm/mach-imx/clk-pllv3.c
to drivers/clk/imx/clk-pllv3.c since the orginal change was made,
so the revert is done to the new file instead.Signed-off-by: Irina Tirdea
(cherry picked from commit dd50ef8f53be467f59947e4f2b3d03c093ec9783) -
This needs to be one individual change since otherwise the driver
and the dtbs won't build anymore. This updates all the dts and dtsi files,
the clock index defines and the imx8mq clock driver itselfSigned-off-by: Abel Vesa
Reviewed-by: Leonard Crestez -
Since a lot of clocks on imx8m are formed by a mux, gate, predivider and
divider, the idea here is to combine all of those into one composite clock,
but we need to deal with both predivider and divider at the same time and
therefore we add the imx8m_clk_composite_divider_ops and register
the composite clock with those.Signed-off-by: Abel Vesa
Suggested-by: Sascha Hauer
Reviewed-by: Sascha Hauer
Acked-by: Leonard Crestez -
The imx/clk-composite is only used by 7ulp. It makes more sense
to mention that in the name of the file and the register function
since later imx-composite clocks may be added.Signed-off-by: Abel Vesa
Reviewed-by: Leonard Crestez -
Moving video pll2 control to the display driver to allow more flexibility
for setting rates.Signed-off-by: Oliver Brown
-
Add i.MX6ULZ clock driver support. i.MX6ULZ clock
tree is same as i.MX6ULL. so reuse the i.MX6ULL
clock compatible check.Signed-off-by: Bai Ping
-
The gpmi clock is from NAND clock root, while aphb-dma clock is from NAND_USDHC_BUS_CLK_ROOT.
Both share same clock gate CCGR_NAND. We use imx_clk_gate2_shared2 to
create two clocks for them.Signed-off-by: Ye Li
Reviewed-by: Bai Ping -
According to ADD, the audio ahb and ipg clock should be in 1:1 mode
and the frequency is 400MHzSigned-off-by: Shengjiu Wang
Reviewed-by: Viorel Suman
(cherry picked from commit ee175a8cea1a7d27954a73c3447bb16edd71f4c8) -
With the 800M clock source, there is noise on SAI5 (PDM, or AK5558)
recording with some chips, but it may be ok for other chips.
The reason is not clear.
This patch is to switch the clock source to 500M.Signed-off-by: Shengjiu Wang
(cherry picked from commit 3f4e34d26ceb8569eeb6cbb2e5a410d0332a9e62) -
Need use LPCG_BASE to wrap the lpcg gate, otherwise XEN DomU
will dump when doing ioremap for the lpcgs, because the lpcg
conflicts with DomU RAM space.Signed-off-by: Peng Fan
(cherry picked from commit caf4564bf4fe70fc6466ce18a84b5c73c80d21a0) -
Signed-off-by: Daniel Baluta
Reviewed-by: Shengjiu Wang
(cherry picked from commit 8bc09ad559237c136f88d93bd696fe10dc4658db) -
Correct lpspi1 scu resource ID.
Reviewed-by: Anson Huang
Signed-off-by: Fugang Duan -
Keep earlycon uart port clocks on during bootconsole enable period
to avoid messy chars print out.Signed-off-by: Fugang Duan
-
Removed the IMX8QM_HDMI_AV_PLL_BYPASS_CLK because it is not supported by SCFW.
Changed the selector array to use the IMX8QM_HDMI_AV_PLL_CLK as the bypass parent.Signed-off-by: Oliver Brown
-
Add a new init-on-array property, the clk driver will
parse this array and prepare enable the related clocks.Previously, the clocks needs to be init on are hardcoded in SoC
clk driver. When we need to support two OSes, some clks
needs to be ini on, however such clocks does not need to be init on
for Single Linux OS environment.At current stage using Jailhouse hypervisor supporting Two Linux OS,
OS1 use SDHC2, OS2 use SDHC3, they share one IMX8MM_CLK_NAND_USDHC_BUS_CG,
because no power management supported, so we need clk_ignore_unused
and make sure this clk being enabled, to make sure the 2nd OS
could has SDHC3 working.The i.MX8MQ also has same code, but there is no good place to hold
it in common place, so duplicate it clk-imx8mm.c for now.Signed-off-by: Peng Fan
(cherry picked from commit 58d25fb00099142f15bcf2a66432b25da75ef38e) -
Remove unused ROMCP clks and related as LPCG
no longer existsSigned-off-by: Teo Hall
Reviewed-by: Anson Huang
(cherry picked from commit 1c15332dffe7e41f0b9d367b96dd426798ec8b06) -
No need to enable IMX7D_NAND_USDHC_BUS_ROOT_CLK during the imx7d clock
driver init, so remove it from the clks_init_on[].Signed-off-by: Haibo Chen
(cherry picked from commit d63d8a2d501ddc93a3406111134242090a713c4a) -
No need to enable IMX8MQ_CLK_NAND_USDHC_BUS_CG during the imx8mq clock driver
init, so remove it from the clks_init_on[].Signed-off-by: Haibo Chen
(cherry picked from commit 6c90e1bfc38eab27921d26b1218993e5cd52a425) -
No need to enable IMX8MM_CLK_NAND_USDHC_BUS_CG during the imx8mm clock driver
init, so remove it from the clks_init_on[].Signed-off-by: Haibo Chen
(cherry picked from commit 7a8f9c1917dec30fc37b6b8ea74461e80ecdbc30) -
No need to enable IMX8MQ_CLK_AUDIO_AHB_DIV during imx8mq clock
driver init, so remove it from the clks_init_on[].Signed-off-by: Viorel Suman
(cherry picked from commit b13900ec3296f579f54581483858cc053d2bbff3) -
No fail when no no_acm node. We do not have np_acm node
for the 2nd OS, so let's ignore np_acm.Also we use partition for the 2nd OS, the registeration of some
clocks are not owned by the 2nd OS, so it will return -ENODEV.
Let's suppress the error message for -ENODEV.Signed-off-by: Peng Fan
Reviewed-by: Bai Ping
(cherry picked from commit 39d196d84ed80237d0d9e669965903c785146727) -
Add a new init-on-array property, the clk driver will
parse this array and prepare enable the related clocks.Previously, the clocks needs to be init on are hardcoded in SoC
clk driver. When we need to support two OSes, some clks
needs to be ini on, however such clocks does not need to be init on
for Single Linux OS environment.At current stage using Jailhouse hypervisor supporting Two Linux OS,
OS1 use SDHC2, OS2 use SDHC0, they share one IMX8MQ_CLK_NAND_USDHC_BUS_CG,
because no power management supported, so we need clk_ignore_unused
and make sure this clk being enabled, to make sure the 2nd OS
could has SDHC0 working.Signed-off-by: Peng Fan
Reviewed-by: Bai Ping
(cherry picked from commit 9e6e0ffe8876d5f52ee372ec438ab30ef01c4a5d) -
On i.MX8MM, it has an dram_alt clock source that can be used when
DDRC clock rate is lower than 667MHz, so add this clock.Signed-off-by: Bai Ping
Reviewed-by: Anson Huang
(cherry picked from commit 303867c769e3c0758b9ee8fcf31d8cc3c632a80d) -
Add LCDIF PLL resource and clocks, and power domain for it.
Add Pixel link clocks and set it from bypass path.
Muxes were added so that the slices can choose the bypass input
(lcd_pxl_bypass_div and elcdif_pll_div).clk summary example:
lcd_pxl_bypass_div 2 2 24000000
lcd_pxl_sel 1 1 24000000
lcd_pxl_div 1 1 24000000
lcd_pxl_clk 1 1 24000000
elcdif_pll_div 1 1 792000000
elcdif_pll 2 2 792000000
lcd_sel 1 1 792000000
lcd_div 1 1 79200000
lcd_clk 1 1 79200000Signed-off-by: Adriana Reus
-
correct the clock name typo.
change the MCLK to use osc_24m.
remove unnecessary rate setting for MCLK in dts file.Signed-off-by: Robby Cai
-
In order to replace the M4_MU# by the LSIO MU in the
RPMSG usage.
Define the clocks of the LSIO MU for iMX8Signed-off-by: Richard Zhu
