10 Sep, 2015
1 commit
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…erry.reding/linux-pwm
Pull pwm updates from Thierry Reding:
"This set of changes introduces the beginnings of a new API that's
based around the concept of states that can be atomically applied.
Drivers go to various lengths to implement something similar, which
indicates that the core should really be providing the necessary
framework.On top of that, there is a bit of cleanup as well as improved
kerneldoc and integration into the device-drivers DocBook.Regarding drivers there is a new one for the NXP LPC18xx family of
SoCs and a couple of fixes for existing drivers (pca9685, Broadcom
Kona and Atmel HLCDC)"* tag 'pwm/for-4.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm:
ARM: at91: pwm: atmel-hlcdc: Add at91sam9n12 errata
pwm: Add NXP LPC18xx PWM/SCT DT binding documentation
pwm: NXP LPC18xx PWM/SCT driver
pwm-pca9685: Support changing the output frequency
pwm-pca9685: Fix several driver bugs
pwm: kona: Modify settings application sequence
pwm: pca9685: Drop owner assignment
pwm: Add to device-drivers documentation
pwm: Clean up kerneldoc
pwm: Remove useless whitespace
pwm: sysfs: Remove unnecessary padding
pwm: sysfs: Properly convert from enum to string
pwm: Make use of pwm_get_xxx() helpers where appropriate
pwm: Add pwm_get_polarity() helper function
pwm: Constify PWM device where possible
pwm: Add the pwm_is_enabled() helper
09 Sep, 2015
2 commits
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The errata for HLCDC PWM of at91sam9n12 are the same as for at91sam9x5.
Signed-off-by: Josh Wu
Acked-by: Alexandre Belloni
Signed-off-by: Thierry Reding -
This commit adds support for NXP LPC18xx PWM/SCT.
NXP LPC SoCs family, which includes LPC18xx/LPC43xx, provides a State
Configurable Timer (SCT) which can be configured as a Pulse Width
Modulator. Other SoCs in that family may share the same hardware.The PWM supports a total of 16 channels, but only 15 can be simultaneously
requested. There's only one period, global to all the channels, thus PWM
driver will refuse setting different values to it, unless there's only one
channel requested.Signed-off-by: Ariel D'Alessandro
[thierry.reding@gmail.com: remove excessive padding of fields]
Signed-off-by: Thierry Reding
17 Aug, 2015
6 commits
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Previously, period_ns and duty_ns were only used to determine the
ratio of ON and OFF time, the default frequency of 200 Hz was never
changed.
The PCA9685 however is capable of changing the PWM output frequency,
which is expected when changing the period.This patch configures the prescaler accordingly, using the formula
and notes provided in the PCA9685 datasheet.
Bounds checking for the minimum and maximum frequencies, last updated
in revision v.4 of said datasheet, is also added.The prescaler is only touched if the period changed, because we have to
put the chip into sleep mode to unlock the prescale register.
If it is changed, the PWM output frequency changes for all outputs,
because there is one prescaler per chip. This is documented in the
PCA9685 datasheet and in the comments.If the duty cycle is not changed at the same time as the period, then
we restart the PWM output using the duty cycle to period ratio from
before the period change.
When using LEDs for example, previously set brightness levels stay the
same when the frequency changes.Cc: Thierry Reding
Cc: Steffen Trumtrar
Signed-off-by: Clemens Gruber
Signed-off-by: Thierry Reding -
Problems:
- When duty_ns == period_ns, the full OFF bit was not cleared and the
PWM output of the PCA9685 stayed off.
- When duty_ns == period_ns and the catch-all channel was used, the
ALL_LED_OFF_L register was not cleared.
- The full ON bit was not cleared when setting the OFF time, therefore
the exact OFF time was ignored when setting a duty_ns < period_nsSolution: Clear both OFF registers when setting full ON and clear the
full ON bit when changing the OFF registers.Cc: Thierry Reding
Cc: Steffen Trumtrar
Signed-off-by: Clemens Gruber
Signed-off-by: Thierry Reding -
Update the driver so that settings are applied in accordance with the
most recent version of the hardware spec. The revised sequence clears
the trigger bit, waits 400ns, writes settings, sets the trigger bit,
and waits another 400ns. This corrects an issue where occasionally a
requested change was not properly reflected in the PWM output.Reviewed-by: Arun Ramamurthy
Reviewed-by: Scott Branden
Tested-by: Scott Branden
Reviewed-by: Tim Kryger
Signed-off-by: Jonathan Richardson
Signed-off-by: Thierry Reding -
i2c_driver does not need to set an owner because i2c_register_driver()
will set it.Signed-off-by: Krzysztof Kozlowski
Signed-off-by: Thierry Reding -
Clean up kerneldoc in preparation for including the PWM documentation in
DocBook.Signed-off-by: Thierry Reding
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Remove useless tabs used for padding in structure definitions as well as
some blank lines.Signed-off-by: Thierry Reding
27 Jul, 2015
2 commits
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Padding initializers so that assignment operators align is bound to lead
to inconsistencies or churn. Single spaces around the assignment is just
fine.Signed-off-by: Thierry Reding
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The current code will check for polarity in a boolean way. While it is
correct that polarity is either normal or inversed, make it more obvious
that it's an enumeration by using a switch statement and explicit
matches on the enumeration values.Signed-off-by: Thierry Reding
21 Jul, 2015
1 commit
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The Crystalcove PMIC provides three PWM signals and this driver exports
one of them on the BYT platform which is used to control backlight for
DSI panel. This is platform device implementation of the drivers/mfd
cell device for CRC PMIC.CC: Samuel Ortiz
Cc: Linus Walleij
Cc: Alexandre Courbot
Cc: Thierry Reding
Cc: Paul Bolle
Cc: Paul Gortmaker
Tested-by: Ville Syrjälä
Signed-off-by: Shobhit Kumar
Reviewed-by: Varka Bhadram
Signed-off-by: Daniel Vetter
20 Jul, 2015
2 commits
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Use the pwm_get_xxx() helpers instead of directly accessing the fields
in struct pwm_device. This will allow us to smoothly move to the atomic
update approach.Signed-off-by: Boris Brezillon
Signed-off-by: Thierry Reding -
Some PWM drivers are testing the PWMF_ENABLED flag. Create a helper
function to hide the logic behind enabled test. This will allow us to
smoothly move from the current approach to an atomic PWM update
approach.Signed-off-by: Boris Brezillon
Signed-off-by: Thierry Reding
24 Jun, 2015
1 commit
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…erry.reding/linux-pwm
Pull pwm updates from Thierry Reding:
"This has a couple of fixes for Atmel, Samsung and Broadcom drivers.Some preparatory patches for more upcoming Intel work is included as
well"* tag 'pwm/for-4.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm:
pwm: lpss: pci: Add support for Broxton platform
pwm: bcm-kona: Don't set polarity in probe
pwm: Add pwmchip_add_with_polarity() API
pwm: atmel: Fix incorrect CDTY value after disabling
pwm: atmel: Fix incorrect CDTY value after enabling
pwm: samsung: Use MODULE_DEVICE_TABLE() to include OF modalias
pwm: Add support to remove registered consumer lookup tables
12 Jun, 2015
5 commits
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Add PCI device IDs for Broxton platform.
Signed-off-by: Qipeng Zha
Acked-by: Mika Westerberg
Signed-off-by: Thierry Reding -
Omit setting the polarity to normal during probe and instead use the new
pwmchip_add_with_polarity() function to register a PWM chip with inverse
polarity by default for all channels to reflect the hardware default.Signed-off-by: Arun Ramamurthy
Reviewed-by: Ray Jui
Signed-off-by: Scott Branden
Signed-off-by: Tim Kryger
Signed-off-by: Jonathan Richardson
[thierry.reding@gmail.com: use pwmchip_add_with_polarity()]
Signed-off-by: Thierry Reding -
Add a new function to register a PWM chip with channels that have their
initial polarity as specified by an additional parameter. This benefits
drivers of controllers that by default operate with inversed polarity
by removing the need to modify the polarity during initialization.Signed-off-by: Tim Kryger
Signed-off-by: Jonathan Richardson
[thierry.reding@gmail.com: export pwmchip_add_with_polarity()]
Signed-off-by: Thierry Reding -
pwm-leds calls .config() and .disable() in a row. This exhibits that it
may happen that the channel gets disabled before CDTY has been updated
with CUPD. The issue gets quite worse with long periods. So, ensure that
at least one period has past before disabling the channel by polling
ISR.Signed-off-by: Alexandre Belloni
Acked-by: Nicolas Ferre
Tested-by: Gaël PORTAY
Signed-off-by: Thierry Reding -
CUPD is not flushed before enabling the channel so it will update
CDTY/CPRD just after one period. So we always set CUPD, even when the
channel is not enabled.Signed-off-by: Alexandre Belloni
Acked-by: Nicolas Ferre
Signed-off-by: Thierry Reding
21 May, 2015
1 commit
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If the pwm-samsung driver is built as a module, modalias information is
not filled so the module is not autoloaded. Use the MODULE_DEVICE_TABLE()
macro to export the OF device ID so the module contains that information.Signed-off-by: Javier Martinez Canillas
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Thierry Reding
19 May, 2015
1 commit
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The PWM hardware on Pistachio platform has a maximum timebase steps
value to 255. To fix it, let's introduce a compatible-specific
data structure to contain the SoC-specific details and use it to
specify a maximum timebase.Also, let's limit the minimum timebase to 16 steps, to allow a sane
range of duty cycle steps.Fixes: 277bb6a29e00 ("pwm: Imagination Technologies PWM DAC driver")
Signed-off-by: Naidu Tellapati
Signed-off-by: Ezequiel Garcia
Signed-off-by: Thierry Reding
06 May, 2015
1 commit
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In case some drivers are unloading, they can remove lookup tables which
they had registered during their load time to avoid redundant entries if
loaded again.CC: Samuel Ortiz
Cc: Linus Walleij
Cc: Alexandre Courbot
Cc: Thierry Reding
Signed-off-by: Shobhit Kumar
Signed-off-by: Thierry Reding
23 Apr, 2015
1 commit
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For platforms that don't support DT, some early MFD modules can register
lookup tables. Remove the __init annotation so that this works. This is
similar to gpio_add_lookup_table() which allows late additions.CC: Samuel Ortiz
Cc: Linus Walleij
Cc: Alexandre Courbot
Cc: Thierry Reding
Signed-off-by: Shobhit Kumar
Signed-off-by: Thierry Reding
27 Mar, 2015
1 commit
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When disabling the Samsung PWM the output state remains at the level it
was at the end of a PWM cycle. In other words, calling pwm_disable()
when at 100% duty cycle will keep the output active, while at all other
settings the output will go/stay inactive. On top of that the Samsung
PWM settings are double-buffered, which means the new settings only get
applied at the start of a new PWM cycle.This results in a race if the PWM is at 100% duty cycle and a driver
calls:pwm_config(pwm, 0, period);
pwm_disable(pwm);In this case the PWMs output will unexpectedly stay active, unless a new
PWM cycle happened to start between the register writes in pwm_config()
and pwm_disable(). As far as I can tell this is a regression introduced
by 3bdf878, before that a call to pwm_config() would call
pwm_samsung_enable() which, while heavy-handed, made sure the expected
settings were live.To resolve this, while not re-introducing the issues 3bdf878 (flickering
as the PWM got reset while in a PWM cycle) fixed, only force an update
of the settings when at 100% duty cycle, which shouldn't have any
noticeable effect on the output but is enough to ensure the behaviour is
as expected on disable.Signed-off-by: Sjoerd Simons
Reviewed-by: Javier Martinez Canillas
Acked-by: Lukasz Majewski
Signed-off-by: Thierry Reding
11 Mar, 2015
3 commits
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The driver computes which clock divider it sould be using from the
requested period. This computation assumes that the link between the
register value and the actual divider value is raising 2 to the power of
the registry value.div = 1 << regvalue
This is true only for the first 5 values out of 8. Next values are 64,
256 and, 1024 - instead of 32, 64, 128.
This affects only the users requesting a period > 0.04369s.Replace the computation with a look-up table.
Signed-off-by: Gaetan Hug
Acked-by: Shawn Guo
Signed-off-by: Thierry Reding -
sama5d4 SoC also has an errata on the HLCDC PWM. It is the same as the
sama5d3 that is forbidding the use of div1 prescaler.Signed-off-by: Nicolas Ferre
Acked-by: Boris Brezillon
Signed-off-by: Thierry Reding -
The regmap_config struct may be const because it is not modified by the
driver and regmap_init() accepts pointer to const.Signed-off-by: Krzysztof Kozlowski
Signed-off-by: Thierry Reding
18 Feb, 2015
1 commit
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Instead of using the literal value for the number of nanoseconds per
second, use the macro instead to increase readability.Signed-off-by: Thierry Reding
03 Feb, 2015
1 commit
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The of_node_put() function tests whether its argument is NULL and then
returns immediately. Thus the test around the call is not needed.This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring
Signed-off-by: Thierry Reding
30 Jan, 2015
5 commits
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The Pistachio SOC from Imagination Technologies includes a Pulse Width
Modulation DAC which produces 1 to 4 digital bit-outputs which represent
digital waveforms. These PWM outputs are primarily in charge of controlling
backlight LED devices.Reviewed-by: Andrew Bresticker
Signed-off-by: Naidu Tellapati
Signed-off-by: Sai Masarapu
Signed-off-by: Ezequiel Garcia
Reviewed-by: Vladimir Zapolskiy
[thierry.reding: fixup license header as discussed on list]
Signed-off-by: Thierry Reding -
This patch introduces a bitmap which is used to keep track of the
pwm channels which have been configured in a pwm chip.The method used earlier to find the number of configured channels,
was to count the pwmdevices with PWMF_REQUESTED field set
and period value configured. This was not correct and failed
when of_pwm_get()/pwm_get() and then pwm_config() was used.Signed-off-by: Ajit Pal Singh
Signed-off-by: Thierry Reding -
This adds a generic PWM framework driver for the PWM controller
found on Allwinner SoCs.Signed-off-by: Alexandre Belloni
Acked-by: Maxime Ripard
Signed-off-by: Thierry Reding -
The slow and system clock should never return a rate of zero, but this
might happen if the clocks property defined in the DT is referencing the
wrong clocks.Prevent any division by zero from happening by testing the clk_freq
value before calling do_div().Signed-off-by: Boris Brezillon
Signed-off-by: Thierry Reding -
The include/linux/clk.h header defines dummy implementations for the
various clk_*() functions if HAVE_CLK is not selected to improve build
coverage in randconfig builds.The dummy implementation of clk_get_rate() returns 0, which causes the
Atmel HLCDC PWM driver's atmel_hlcdc_pwm_config() implementation to end
up calling:do_div(clk_period_ns, 0)
On x86, do_div(n, base) will end up evaluating to this:
n >>= ilog2(base)
with base = 0, the implementation of ilog2() will call ____ilog2_NaN(),
which is purposely undefined and results in a linker failure:ERROR: "____ilog2_NaN" [drivers/pwm/pwm-atmel-hlcdc.ko] undefined!
The implementation of do_div() checks that base is a power of 2 before
calling ilog2(). The compiler doesn't optimize this away, presumably
because is_power_of_2() is an inline function and the compiler doesn't
or can't inspect it closely enough. ilog2() being a macro it still ends
up generating the ____ilog2_NaN() because of the constant 0.The root of the problem is that the driver really should be checking
before possibly dividing by zero. That should eventually be fixed, but
for now just assume that the clock runs at a sensible frequency when
available.Reported-by: Jim Davis
Acked-by: Boris Brezillon
Signed-off-by: Thierry Reding
18 Dec, 2014
1 commit
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…ierry.reding/linux-pwm
Pull pwm updates from Thierry Reding:
"There are two new drivers, one for the BCM2835 (Raspberry Pi) and one
used in conjunction with the LCD controller on various Atmel SoCs.
The Samsung PWM driver can now be built for 64-bit ARM (Exynos7).A couple of fixes have been applied to the FTM PWM driver and system
sleep support was added"* tag 'pwm/for-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm:
pwm: atmel-hlcdc: add at91sam9x5 and sama5d3 errata handling
pwm: ftm: Add Power Management support for FTM PWM
pwm: ftm: Add regmap rbtree type cache support
pwm: ftm: Correctly track usage count
pwm: samsung: Allow Samsung PWM driver to be enabled on Exynos7
pwm: add DT bindings documentation for atmel-hlcdc-pwm driver
pwm: add support for atmel-hlcdc-pwm device
pwm: Add BCM2835 PWM driver
04 Dec, 2014
1 commit
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at91sam9x5 has an errata forbidding the use of slow clk as a clk source and
sama5d3 SoCs has another errata forbidding the use of div1 prescaler.Take both of these erratas into account.
Signed-off-by: Boris Brezillon
Acked-by: Nicolas Ferre
Signed-off-by: Thierry Reding
01 Dec, 2014
3 commits
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Add PM support for FTM PWM driver using callback function suspend
and resume in .driver.pm of platform_driver.Signed-off-by: Xiubo Li
Signed-off-by: Thierry Reding -
This patch is to prepare for adding PM support for FTM PWM driver using
callback function suspend and resume in .driver.pm of platform_driver.Signed-off-by: Xiubo Li
Signed-off-by: Thierry Reding -
No matter how many times the FTM PWM is enabled, the use_count will
always be one.Signed-off-by: Xiubo Li
Signed-off-by: Thierry Reding
