30 Aug, 2017
1 commit
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In order to make sure that get the regulator correctly.
Check the return value of devm_regulator_get().
Return value directly if it is '-EPROBE_DEFER'Signed-off-by: Richard Zhu
(cherry picked from commit 25df25ae44f4d9799c49476516a955b66d5ea9dc)
16 Jun, 2017
1 commit
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iMX7D Sabre SD board implement the GPIO expander
connected to a peripheral bus.
Probe deferral would be triggered when try to request
the expanded GPIO at the first time.
pcie ep can't be probed properly at the second probe,
because of the duplicated registration of the sysfs.Change the registeration point of the sysfs to fix
this issue.Signed-off-by: Richard Zhu
(cherry picked from commit dfa403d5ae689fcb9cdb8e082ad15493bf8a38d7)
09 Jun, 2017
5 commits
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Some designs implement reset GPIO via a GPIO expander connected to a
peripheral bus. One such example would be i.MX7 Sabre board where said
GPIO is provided by SPI shift register connected to a bitbanged SPI bus.
To support such designs, allow reset GPIO request to defer probing of the
driver.Signed-off-by: Andrey Smirnov
Signed-off-by: Bjorn Helgaas
Reviewed-by: Lucas Stach
Cc: yurovsky@gmail.com
Cc: Fabio Estevam
Cc: Dong Aisheng
Cc: linux-arm-kernel@lists.infradead.org
(cherry picked from commit bde4a5a00e761f55be92f62378cf5024ced79ee3) -
The mem_base address is configured as the outbound
memory region twice when imx pcie ep/rc validation
is enabled.
Mask the one contained in desigware driver to fix
this issue.
Remove the usleep_range usage in designware driver,
since that function maybe used in imx noirq pm
calls.Signed-off-by: Richard Zhu
-
pp->ops is not assigned properly, thus there
would be kernel panic when reboot ep board.
Initialized pp->ops in ep initializatione,
fix this issue.
don't call dw_pcie_wait_for_link because
the usleep is used in it.Signed-off-by: Richard Zhu
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imxcommunity reports that Intel Wireless 3160 doesn't
work if the perst# is toggled before the release of rc
controller's reset.Specification doesn't specify the exactly sequence of
the toggle of the perst# and the release of the rc
controller reset. Just find the following description
in the chapter 4.2.2 of the PCI Local Bus Specification."The system must guarantee that the bus remains in the idle
state for a minimum time delay following the deassertion
of RST# to a device before the system will permit the first
assertion of FRAME#."Toggle the perst# after the release of rc's reset to
fix the issue.Signed-off-by: Richard Zhu
(cherry picked from commit ba75c5e4795ab36d7765fe3ac03f0c4320828c78) -
In the imx pcie ep/rc validation system, the mem
resource parser of ep probe is failed on 4.9.
Change the mem resource parser method from 4.1
to 4.9 to fix this failure.Signed-off-by: Richard Zhu
08 Jun, 2017
6 commits
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Remove the redundant codes in pcie-designware driver.
Because that the class configration had been
contained in 4.9 kernel.Signed-off-by: Richard Zhu
-
- Do not return error when the GEN2 link negatiation
is failed. Because that the limitation maybe caused
by the remote GEN1 EP device.
- Move the power saving codes to the proper place
after the link is down.
Otherwise, system would hang when link is down.Signed-off-by: Richard Zhu
-
Description: Initial VCO oscillation may fail under
corner conditions such as cold temperature. It causes
PCIe PLL fail to lock in initialization phase.Project Impact: iMX7 PCIe PLL fails to lock and iMX7D
PCIe doesn't work.Workarounds: To toggle internal PLL_PD signal to make
VCO oscillate after G_RST signal is de-asserted by
following the sequences:
- De-asserted G_RST signal
- Toggle internal PLL_PD signal:
- Write "0x04" to the address "0x306D_0054"
- Write "0xA4" to the address "0x306D_0054"
- Write "0x04" to the address "0x306D_0054"
- De-asserted CMN_RST signalSigned-off-by: Richard Zhu
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The ep rc validation is failed on imx6dl.
Root cause:
The ref clk of imx6dl pcie is 100M(bit20 of PLL_ENET).
But the driver doesn't enable it.
Solution:
enable pci_bus clock in ep rc validation system, since
the parent of the pci_bus is the 100M.
The connection between ep and rc only have the TX/RX
parirs, there is no impaction when enable the pcie_bus
in pcie ep rc validation system.Signed-off-by: Richard Zhu
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In order to pass the pcie gen2 compliance tests,
the external oscillator is mandatory required by
imx6 legacy platforms.
add the external osc support by this patch.
- pll6 should be set bypass mode.
- src of the pll6_bypass should be lvds_clk1
- adjust the swing/deemphase value
- re-configure the phy if the external 100Mhz
differential osc is used. Because that phy used
the 125Mhz before.Signed-off-by: Richard Zhu
-
On imx6qp sabresd rev b board, there is a standalone
external oscilator, used to provided the clks for
imx6qp pcie.Add one regulator into pcie node, let the ext osc work.
Signed-off-by: Richard Zhu
23 Feb, 2017
9 commits
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In order to save power consumption, turn off pcie clks/regulators
if there is no pcie link at all.
Summit this patch, because of that MLK-12278
doesn't turn off the clks/regulators actually.Signed-off-by: Richard Zhu
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In order to save power assumption, turn off the pcie clks
when there is no pcie link up at all.
add the option CONFIG_PCI_IMX6_COMPLIANCE_TEST, enable it
when the image is used to do the pcie compliance testsSigned-off-by: Richard Zhu
-
imx pcie used the wrab mode to do the cached access
methods on axi bus. There is 64bytes address mis-aligned
problem.
Disable the cached operations.Signed-off-by: Richard Zhu
(cherry picked from commit 85db70336ab66136481926bcd7f5abe599e2aa4f) -
enable imx6qp pcie support
Signed-off-by: Richard Zhu
-
enable imx6sx pci support
Signed-off-by: Richard Zhu
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Regarding to the limitation of the iMX ADAP(pcie connector),
only imx7d 12x12 arm2 board is used to verify the pcie
ep/rc validation system on imx7d platformsEnalbe the msi pcie ep rc on it.
Test howto:
- Enable CONFIG_PCI_MSI=y, when rebuild the rc/ep images- EP side(console command and kernel message):
root@imx6sxsabresd:~# ./memtool -32 =0
Writing 32-bit value 0x0 to address- RC side(console command and kernel message):
root@imx6sxsabresd:~# cat /proc/interrupts | grep MSI
384: 1 PCI-MSINote:
imx6q msi_addr 0x01ff_8000
imx6sx msi_addr 0x08ff_8000
imx7d msi_addr 0x4ffc_0000Signed-off-by: Richard Zhu
-
Regarding to the limitation of the iMX ADAP(pcie connector),
only imx7d 12x12 arm2 board is used to verify the pcie
ep/rc validation system on imx7d platformshw setup:
* two imx boards, one is used as pcie rc, the other is used
as pcie ep. Connected by fsl pcie adap adaptor.sw setup:
* when build rc image, make sure that
CONFIG_IMX_PCIE=y
# CONFIG_EP_MODE_IN_EP_RC_SYS is not set
CONFIG_RC_MODE_IN_EP_RC_SYS=y
* when build ep image
CONFIG_IMX_PCIE=y
CONFIG_EP_MODE_IN_EP_RC_SYS=y
# CONFIG_RC_MODE_IN_EP_RC_SYS is not setfeatures:
* set-up link between rc and ep by their stand-alone
ref clk running internally.* in ep's system, ep can access the reserved ddr memory
(default address:0x4000_0000 on imx6q sd board, and
0xb000_0000 on imx6sx sdb and imx7d arm2 boards) of
pcie rc's system, by the interconnection between pcie
ep and pcie rc.* add the configuration methods in the ep side, used to
configure the start address and the size of the reserved
rc's memory window.
- cat /sys/devices/soc0/soc.1/1ffc000.pcie/rc_memw_info
- echo 0x41000000 > /sys/devices/soc0/soc.1/1ffc000.pcie/rc_memw_start_set
- echo 0x200000 > /sys/devices/soc0/soc.1/1ffc000.pcie/rc_memw_size_set* provide one example, howto configure the bar# and so on,
when pcie ep emaluates one memory ram ep device* setup one new outbound memory region at rc side, used
to let imx pcie rc can access the memory of imx pcie ep
in imx pcie rc ep validation system.
- set the default address of the ddr memory to be 0x4000_0000
on imxq sd board, and 0xb000_0000 on imx6sx sdb and imx7d
arm2 boards.NOTE:
* boot up ep platform firstly, then boot up rc platform.
* make sure that mem=768M is contained in the kernel command line,
since the start address of the upper 256mb of the 1g ddr mem is
reserved to do the pcie ep rc access operations in default.Test howto of the RC access memory of EP on imx6q sd platforms.
step1:
EP side:
1.1:
echo > /sys/devices/.../pcie/ep_bar0_addr1.2:
memtool -32 4
E
Reading 0x4 count starting at address 0x40000000: 6FE9E9F6 7583FBB9 39EAEFEA FBDCFD78
step2:
RC side:
memtool -32 =58D454DA
memtool -32 =7332095Bstep3:
EP side:
memtool -32 4
E
Reading 0x4 count starting at address 0x40000000: 58D454DA 7332095B 39EAEFEA FBDCFD78
Signed-off-by: Richard Zhu
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- enable pcie functions on imx7d platforms
- grst/brst should be asserted/de-asserted during resume,
since the pcie power would be cut off automatically by HW
during system suspend/resumeSigned-off-by: Richard Zhu
-
- move "program correct class for RC" from dw_pcie_host_init()
to dw_pcie_setup_rc(). since this is RC setup, it's
better to contained in dw_pcie_setup_rc function.
Then, RC can be re-setup really by dw_pcie_setup_rc().
- add one store/re-store msi cfg functions. Because that
pcie controller maybe powered off during system suspend,
and the msi data configuration would be lost.
these functions can be used to store/restore the msi data
and msi_enable during the suspend/resume callback.Signed-off-by: Richard Zhu
09 Feb, 2017
1 commit
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commit 030305d69fc6963c16003f50d7e8d74b02d0a143 upstream.
In a struct pcie_link_state, link->root points to the pcie_link_state of
the root of the PCIe hierarchy. For the topmost link, this points to
itself (link->root = link). For others, we copy the pointer from the
parent (link->root = link->parent->root).Previously we recognized that Root Ports originated PCIe hierarchies, but
we treated PCI/PCI-X to PCIe Bridges as being in the middle of the
hierarchy, and when we tried to copy the pointer from link->parent->root,
there was no parent, and we dereferenced a NULL pointer:BUG: unable to handle kernel NULL pointer dereference at 0000000000000090
IP: [] pcie_aspm_init_link_state+0x170/0x820Recognize that PCI/PCI-X to PCIe Bridges originate PCIe hierarchies just
like Root Ports do, so link->root for these devices should also point to
itself.Fixes: 51ebfc92b72b ("PCI: Enumerate switches below PCI-to-PCIe bridges")
Link: https://bugzilla.kernel.org/show_bug.cgi?id=193411
Link: https://bugzilla.opensuse.org/show_bug.cgi?id=1022181
Tested-by: lists@ssl-mail.com
Tested-by: Jayachandran C.
Signed-off-by: Bjorn Helgaas
Signed-off-by: Greg Kroah-Hartman
26 Jan, 2017
2 commits
-
commit 51ebfc92b72b4f7dac1ab45683bf56741e454b8c upstream.
A PCI-to-PCIe bridge (a "reverse bridge") has a PCI or PCI-X primary
interface and a PCI Express secondary interface. The PCIe interface is a
Downstream Port that originates a Link. See the "PCI Express to PCI/PCI-X
Bridge Specification", rev 1.0, sections 1.2 and A.6.The bug report below involves a PCI-to-PCIe bridge and a PCIe switch below
the bridge:00:1e.0 Intel 82801 PCI Bridge to [bus 01-0a]
01:00.0 Pericom PI7C9X111SL PCIe-to-PCI Reversible Bridge to [bus 02-0a]
02:00.0 Pericom Device 8608 [PCIe Upstream Port] to [bus 03-0a]
03:01.0 Pericom Device 8608 [PCIe Downstream Port] to [bus 0a]01:00.0 is configured as a PCI-to-PCIe bridge (despite the name printed by
lspci). As we traverse a PCIe hierarchy, device connections alternate
between PCIe Links and internal Switch logic. Previously we did not
recognize that 01:00.0 had a secondary link, so we thought the 02:00.0
Upstream Port *did* have a secondary link. In fact, it's the other way
around: 01:00.0 has a secondary link, and 02:00.0 has internal Switch logic
on its secondary side.When we thought 02:00.0 had a secondary link, the pci_scan_slot() ->
only_one_child() path assumed 02:00.0 could have only one child, so 03:00.0
was the only possible downstream device. But 03:00.0 doesn't exist, so we
didn't look for any other devices on bus 03.Booting with "pci=pcie_scan_all" is a workaround, but we don't want users
to have to do that.Recognize that PCI-to-PCIe bridges originate links on their secondary
interfaces.Link: https://bugzilla.kernel.org/show_bug.cgi?id=189361
Fixes: d0751b98dfa3 ("PCI: Add dev->has_secondary_link to track downstream PCIe links")
Tested-by: Blake Moore
Signed-off-by: Bjorn Helgaas
Signed-off-by: Greg Kroah-Hartman -
commit a782b5f986c3fa1cfa7f2b57941200c6a5809242 upstream.
Previously we checked for iATU unroll support by reading PCIE_ATU_VIEWPORT
even on platforms, e.g., Keystone, that do not have ATU ports. This can
cause bad behavior such as asynchronous external aborts:OF: PCI: MEM 0x60000000..0x6fffffff -> 0x60000000
Unhandled fault: asynchronous external abort (0x1211) at 0x00000000
pgd = c0003000
[00000000] *pgd=80000800004003, *pmd=00000000
Internal error: : 1211 [#1] PREEMPT SMP ARM
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.9.0-00009-g6ff59d2-dirty #7
Hardware name: Keystone
task: eb878000 task.stack: eb866000
PC is at dw_pcie_setup_rc+0x24/0x380
LR is at ks_pcie_host_init+0x10/0x170Move the dw_pcie_iatu_unroll_enabled() check so we only call it on
platforms that do not use the ATU. These platforms supply their own
->rd_other_conf() and ->wr_other_conf() methods.[bhelgaas: changelog]
Fixes: a0601a470537 ("PCI: designware: Add iATU Unroll feature")
Fixes: 416379f9ebde ("PCI: designware: Check for iATU unroll support after initializing host")
Tested-by: Kishon Vijay Abraham I
Signed-off-by: Murali Karicheri
Signed-off-by: Bjorn Helgaas
Acked-By: Joao Pinto
Signed-off-by: Greg Kroah-Hartman
12 Jan, 2017
8 commits
-
commit 99e5cde5eae78bef95bfe7c16ccda87fb070149b upstream.
Make sure to drop any device reference taken by vio_find_node() when
adding and removing virtual I/O slots.Fixes: 5eeb8c63a38f ("[PATCH] PCI Hotplug: rpaphp: Move VIO registration")
Signed-off-by: Johan Hovold
Signed-off-by: Michael Ellerman
Signed-off-by: Greg Kroah-Hartman -
commit 1c7de2b4ff886a45fbd2f4c3d4627e0f37a9dd77 upstream.
There is at least one Chelsio 10Gb card which uses VPD area to store some
non-standard blocks (example below). However pci_vpd_size() returns the
length of the first block only assuming that there can be only one VPD "End
Tag".Since 4e1a635552d3 ("vfio/pci: Use kernel VPD access functions"), VFIO
blocks access beyond that offset, which prevents the guest "cxgb3" driver
from probing the device. The host system does not have this problem as its
driver accesses the config space directly without pci_read_vpd().Add a quirk to override the VPD size to a bigger value. The maximum size
is taken from EEPROMSIZE in drivers/net/ethernet/chelsio/cxgb3/common.h.
We do not read the tag as the cxgb3 driver does as the driver supports
writing to EEPROM/VPD and when it writes, it only checks for 8192 bytes
boundary. The quirk is registered for all devices supported by the cxgb3
driver.This adds a quirk to the PCI layer (not to the cxgb3 driver) as the cxgb3
driver itself accesses VPD directly and the problem only exists with the
vfio-pci driver (when cxgb3 is not running on the host and may not be even
loaded) which blocks accesses beyond the first block of VPD data. However
vfio-pci itself does not have quirks mechanism so we add it to PCI.This is the controller:
Ethernet controller [0200]: Chelsio Communications Inc T310 10GbE Single Port Adapter [1425:0030]This is what I parsed from its VPD:
===
b'\x82*\x0010 Gigabit Ethernet-SR PCI Express Adapter\x90J\x00EC\x07D76809 FN\x0746K'
0000 Large item 42 bytes; name 0x2 Identifier String
b'10 Gigabit Ethernet-SR PCI Express Adapter'
002d Large item 74 bytes; name 0x10
#00 [EC] len=7: b'D76809 '
#0a [FN] len=7: b'46K7897'
#14 [PN] len=7: b'46K7897'
#1e [MN] len=4: b'1037'
#25 [FC] len=4: b'5769'
#2c [SN] len=12: b'YL102035603V'
#3b [NA] len=12: b'00145E992ED1'
007a Small item 1 bytes; name 0xf End Tag0c00 Large item 16 bytes; name 0x2 Identifier String
b'S310E-SR-X '
0c13 Large item 234 bytes; name 0x10
#00 [PN] len=16: b'TBD '
#13 [EC] len=16: b'110107730D2 '
#26 [SN] len=16: b'97YL102035603V '
#39 [NA] len=12: b'00145E992ED1'
#48 [V0] len=6: b'175000'
#51 [V1] len=6: b'266666'
#5a [V2] len=6: b'266666'
#63 [V3] len=6: b'2000 '
#6c [V4] len=2: b'1 '
#71 [V5] len=6: b'c2 '
#7a [V6] len=6: b'0 '
#83 [V7] len=2: b'1 '
#88 [V8] len=2: b'0 '
#8d [V9] len=2: b'0 '
#92 [VA] len=2: b'0 '
#97 [RV] len=80: b's\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00'...
0d00 Large item 252 bytes; name 0x11
#00 [VC] len=16: b'122310_1222 dp '
#13 [VD] len=16: b'610-0001-00 H1\x00\x00'
#26 [VE] len=16: b'122310_1353 fp '
#39 [VF] len=16: b'610-0001-00 H1\x00\x00'
#4c [RW] len=173: b'\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00'...
0dff Small item 0 bytes; name 0xf End Tag10f3 Large item 13315 bytes; name 0x62
!!! unknown item name 98: b'\xd0\x03\x00@`\x0c\x08\x00\x00\x00\x00\x00\x00\x00\x00\x00'
===Signed-off-by: Alexey Kardashevskiy
Signed-off-by: Bjorn Helgaas
Signed-off-by: Greg Kroah-Hartman -
commit 1600f62534b7b3da7978b43b52231a54c24df287 upstream.
Mellanox devices were marked as having INTx masking ability broken. As a
result, the VFIO driver fails to start when more than one device function
is passed-through to a VM if both have the same INTx pin.Prior to Connect-IB, Mellanox devices exposed to the operating system one
PCI function per all ports. Starting from Connect-IB, the devices are
function-per-port. When passing the second function to a VM, VFIO will
fail to start.Exclude ConnectX-4, ConnectX4-Lx and Connect-IB from the list of Mellanox
devices marked as having broken INTx masking:- ConnectX-4 and ConnectX4-LX firmware version is checked. If INTx
masking is supported, we unmark the broken INTx masking.
- Connect-IB does not support INTx currently so will not cause any
problem.[bhelgaas: call pci_disable_device() always, after iounmap()]
Fixes: 11e42532ada3 ("PCI: Assume all Mellanox devices have broken INTx masking")
Signed-off-by: Noa Osherovich
Signed-off-by: Bjorn Helgaas
Reviewed-by: Or Gerlitz
Reviewed-by: Gavin Shan
Signed-off-by: Greg Kroah-Hartman -
commit d76d2fe05fd93673d184af77255bbbc63780f4ea upstream.
Change Mellanox's broken_intx_masking() quirk from an "all Mellanox
devices" to a quirk for listed devices only.[bhelgaas: remove #defines, reorder to keep other quirks together]
Signed-off-by: Noa Osherovich
Signed-off-by: Bjorn Helgaas
Reviewed-by: Or Gerlitz
Reviewed-by: Gavin Shan
Signed-off-by: Greg Kroah-Hartman -
commit b88214ce4d7064992452765028bd50702414f15f upstream.
Convert all quirk_broken_intx_masking() quirks from HEADER to FINAL.
The quirk sets dev->broken_intx_masking, which is only used by
pci_intx_mask_supported(), which is not needed until after FINAL
quirks have been run.[bhelgaas: changelog]
Signed-off-by: Noa Osherovich
Signed-off-by: Bjorn Helgaas
Reviewed-by: Gavin Shan
Signed-off-by: Greg Kroah-Hartman -
commit a45e2611b9bbd81288d97d02ce7e74a60a698d43 upstream.
We're trying to mask out bits[23:8] while retaining [32:24, 7:0], but we're
doing the inverse. That doesn't have too much effect, since we're setting
all the [23:8] bits to 1, and the other bits are only relevant for modes
we're currently not using. But we should get this right.Fixes: ca1989084054 ("PCI: rockchip: Fix wrong transmitted FTS count")
Signed-off-by: Brian Norris
Signed-off-by: Bjorn Helgaas
Acked-by: Shawn Lin
Signed-off-by: Greg Kroah-Hartman -
commit 45e9320f3a4ef9588ee50a2eb1891c4bfdbb07df upstream.
The calculation of negotiated lanes is wrong: it should be shifted by
PCIE_CORE_PL_CONF_LANE_SHIFT, but it is shifted by
PCIE_CORE_PL_CONF_LANE_MASK instead. Let's fix it.Fixes: e77f847df54c ("PCI: rockchip: Add Rockchip PCIe controller support")
Signed-off-by: Shawn Lin
Signed-off-by: Bjorn Helgaas
Signed-off-by: Greg Kroah-Hartman -
commit d1d111e073840b8dbc1ae90ba3fc274736451bdc upstream.
If msi_setup_entry() fails to allocate an affinity mask, it logs a message
but continues on and allocates an MSI entry with entry->affinity == NULL.Check for this case in pci_irq_get_affinity() so we don't try to
dereference a NULL pointer.[bhelgaas: changelog]
Fixes: ee8d41e53efe "pci/msi: Retrieve affinity for a vector"
Signed-off-by: Jan Beulich
Signed-off-by: Bjorn Helgaas
Reviewed-by: Christoph Hellwig
CC: Thomas Gleixner
Signed-off-by: Greg Kroah-Hartman
09 Jan, 2017
1 commit
-
commit 6496ebd7edf446fccf8266a1a70ffcb64252593e upstream.
One some systems, the firmware does not allow certain PCI devices to be put
in deep D-states. This can cause problems for wakeup signalling, if the
device does not support PME# in the deepest allowed suspend state. For
example, Pierre reports that on his system, ACPI does not permit his xHCI
host controller to go into D3 during runtime suspend -- but D3 is the only
state in which the controller can generate PME# signals. As a result, the
controller goes into runtime suspend but never wakes up, so it doesn't work
properly. USB devices plugged into the controller are never detected.If the device relies on PME# for wakeup signals but is not capable of
generating PME# in the target state, the PCI core should accurately report
that it cannot do wakeup from runtime suspend. This patch modifies the
pci_dev_run_wake() routine to add this check.Reported-by: Pierre de Villemereuil
Tested-by: Pierre de Villemereuil
Signed-off-by: Alan Stern
Signed-off-by: Bjorn Helgaas
Acked-by: Rafael J. Wysocki
CC: Lukas Wunner
Signed-off-by: Greg Kroah-Hartman
02 Dec, 2016
1 commit
-
Pull PCI fixes from Bjorn Helgaas:
"PCI fixes:- Fix Read Completion Boundary setting, which fixes a boot failure on
IBM x3850 with Mellanox MT27500 ConnectX-3- Update some MAINTAINERS entries and email addresses"
* tag 'pci-v4.9-fixes-4' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
PCI: Set Read Completion Boundary to 128 iff Root Port supports it (_HPX)
PCI: Export pcie_find_root_port
PCI: designware-plat: Update author email
PCI: designware: Change maintainer to Joao Pinto
MAINTAINERS: Add devicetree binding to PCI i.MX6 entry
MAINTAINERS: Update Richard Zhu's email address
24 Nov, 2016
2 commits
-
Per PCIe spec r3.0, sec 2.3.1.1, the Read Completion Boundary (RCB)
determines the naturally aligned address boundaries on which a Read Request
may be serviced with multiple Completions:- For a Root Complex, RCB is 64 bytes or 128 bytes
This value is reported in the Link Control RegisterNote: Bridges and Endpoints may implement a corresponding command bit
which may be set by system software to indicate the RCB value for the
Root Complex, allowing the Bridge/Endpoint to optimize its behavior
when the Root Complex’s RCB is 128 bytes.- For all other system elements, RCB is 128 bytes
Per sec 7.8.7, if a Root Port only supports a 64-byte RCB, the RCB of all
downstream devices must be clear, indicating an RCB of 64 bytes. If the
Root Port supports a 128-byte RCB, we may optionally set the RCB of
downstream devices so they know they can generate larger Completions.Some BIOSes supply an _HPX that tells us to set RCB, even though the Root
Port doesn't have RCB set, which may lead to Malformed TLP errors if the
Endpoint generates completions larger than the Root Port can handle.The IBM x3850 X6 with BIOS version -[A8E120CUS-1.30]- 08/22/2016 supplies
such an _HPX and a Mellanox MT27500 ConnectX-3 device fails to initialize:mlx4_core 0000:41:00.0: command 0xfff timed out (go bit not cleared)
mlx4_core 0000:41:00.0: device is going to be reset
mlx4_core 0000:41:00.0: Failed to obtain HW semaphore, aborting
mlx4_core 0000:41:00.0: Fail to reset HCA
------------[ cut here ]------------
kernel BUG at drivers/net/ethernet/mellanox/mlx4/catas.c:193!After 6cd33649fa83 ("PCI: Add pci_configure_device() during enumeration")
and 7a1562d4f2d0 ("PCI: Apply _HPX Link Control settings to all devices
with a link"), we apply _HPX settings to *all* devices, not just those
hot-added after boot.Before 7a1562d4f2d0, we didn't touch the Mellanox RCB, and the device
worked. After 7a1562d4f2d0, we set its RCB to 128, and it failed.Set the RCB to 128 iff the Root Port supports a 128-byte RCB. Otherwise,
set RCB to 64 bytes. This effectively ignores what _HPX tells us about
RCB.Note that this change only affects _HPX handling. If we have no _HPX, this
does nothing with RCB.[bhelgaas: changelog, clear RCB if not set for Root Port]
Fixes: 6cd33649fa83 ("PCI: Add pci_configure_device() during enumeration")
Fixes: 7a1562d4f2d0 ("PCI: Apply _HPX Link Control settings to all devices with a link")
Link: https://bugzilla.kernel.org/show_bug.cgi?id=187781
Tested-by: Frank Danapfel
Signed-off-by: Johannes Thumshirn
Signed-off-by: Bjorn Helgaas
Acked-by: Myron Stowe
CC: stable@vger.kernel.org # v3.18+ -
Export pcie_find_root_port() so we can use it outside of PCIe-AER error
injection.Signed-off-by: Johannes Thumshirn
Signed-off-by: Bjorn Helgaas
17 Nov, 2016
1 commit
-
I returned to Synopsys and so I am sending this patch to update the email
address of the pcie-designware-plat author.Signed-off-by: Joao Pinto
Signed-off-by: Bjorn Helgaas
15 Nov, 2016
1 commit
-
Pull x86 fixes from Ingo Molnar:
"Misc fixes:- fix an Intel/MID boot crash/hang bug
- fix a cache topology mis-parsing bug on certain AMD CPUs
- fix a virtualization firmware bug by adding a check+quirk
workaround on the kernel side"* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/cpu: Deal with broken firmware (VMWare/XEN)
x86/cpu/AMD: Fix cpu_llc_id for AMD Fam17h systems
x86/platform/intel-mid: Retrofit pci_platform_pm_ops ->get_state hook
12 Nov, 2016
1 commit
-
Pull PCI fixes from Bjorn Helgaas:
- Update MAINTAINERS for Intel VMD driver filename
- Update Rockchip rk3399 host bridge driver DTS and resets
- Fix ROM shadow problem that made some video device initialization
fail* tag 'pci-v4.9-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
PCI: VMD: Update filename to reflect move
arm64: dts: rockchip: add three new resets for rk3399 PCIe controller
PCI: rockchip: Add three new resets as required properties
PCI: Don't attempt to claim shadow copies of ROM