Eric Lee / smarc-fsl-linux-kernel

07 Dec, 2011

2 commits

  • c1d6f42f1   perf, x86: Implement arch event mask as quirk ... Browse Code »

    Implement the disabling of arch events as a quirk so that we can print
    a message along with it. This creates some visibility into the problem
    space and could allow us to work on adding more work-around like the
    AAJ80 one.

    Requested-by: Ingo Molnar
    Cc: Gleb Natapov
    Signed-off-by: Peter Zijlstra
    Link: http://lkml.kernel.org/n/tip-wcja2z48wklzu1b0nkz0a5y7@git.kernel.org
    Signed-off-by: Ingo Molnar

    Peter Zijlstra
     
  • ffb871bc9   x86, perf: Disable non available architectural events ... Browse Code »

    Intel CPUs report non-available architectural events in cpuid leaf
    0AH.EBX. Use it to disable events that are not available according
    to CPU.

    Signed-off-by: Gleb Natapov
    Signed-off-by: Peter Zijlstra
    Link: http://lkml.kernel.org/r/1320929850-10480-7-git-send-email-gleb@redhat.com
    Signed-off-by: Ingo Molnar

    Gleb Natapov
     

06 Dec, 2011

1 commit

  • bc1738f6e   perf, x86: Fix event scheduler for constraints with overlapping counters ... Browse Code »

    The current x86 event scheduler fails to resolve scheduling problems
    of certain combinations of events and constraints. This happens if the
    counter mask of such an event is not a subset of any other counter
    mask of a constraint with an equal or higher weight, e.g. constraints
    of the AMD family 15h pmu:

    counter mask weight

    amd_f15_PMC30 0x09 2 overlap.
    * Reimplementation using perf scheduling helper functions.

    V3:
    * Added WARN_ON_ONCE() if out of save states.
    * Changed function interface of perf_sched_restore_state() to use bool
    as return value.

    Signed-off-by: Robert Richter
    Signed-off-by: Peter Zijlstra
    Cc: Stephane Eranian
    Link: http://lkml.kernel.org/r/1321616122-1533-3-git-send-email-robert.richter@amd.com
    Signed-off-by: Ingo Molnar

    Robert Richter
     

10 Oct, 2011

1 commit

  • 144d31e6f   perf, intel: Use GO/HO bits in perf-ctr ... Browse Code »

    Intel does not have guest/host-only bit in perf counters like AMD
    does. To support GO/HO bits KVM needs to switch EVENTSELn values
    (or PERF_GLOBAL_CTRL if available) at a guest entry. If a counter is
    configured to count only in a guest mode it stays disabled in a host,
    but VMX is configured to switch it to enabled value during guest entry.

    This patch adds GO/HO tracking to Intel perf code and provides interface
    for KVM to get a list of MSRs that need to be switched on a guest entry.

    Only cpus with architectural PMU (v1 or later) are supported with this
    patch. To my knowledge there is not p6 models with VMX but without
    architectural PMU and p4 with VMX are rare and the interface is general
    enough to support them if need arise.

    Signed-off-by: Gleb Natapov
    Signed-off-by: Peter Zijlstra
    Link: http://lkml.kernel.org/r/1317816084-18026-7-git-send-email-gleb@redhat.com
    Signed-off-by: Ingo Molnar

    Gleb Natapov
     

26 Sep, 2011

1 commit

  • de0428a7a   x86, perf: Clean up perf_event cpu code ... Browse Code »

    The CPU support for perf events on x86 was implemented via included C files
    with #ifdefs. Clean this up by creating a new header file and compiling
    the vendor-specific files as needed.

    Signed-off-by: Kevin Winchester
    Signed-off-by: Peter Zijlstra
    Link: http://lkml.kernel.org/r/1314747665-2090-1-git-send-email-kjwinchester@gmail.com
    Signed-off-by: Ingo Molnar

    Kevin Winchester