22 Oct, 2010

1 commit

• 2f0384e5f   Merge branch 'x86-amd-nb-for-linus' of git://git.kernel.org/pub/scm/linux/kernel… ... Browse Code »

  …/git/tip/linux-2.6-tip

  * 'x86-amd-nb-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
  x86, amd_nb: Enable GART support for AMD family 0x15 CPUs
  x86, amd: Use compute unit information to determine thread siblings
  x86, amd: Extract compute unit information for AMD CPUs
  x86, amd: Add support for CPUID topology extension of AMD CPUs
  x86, nmi: Support NMI watchdog on newer AMD CPU families
  x86, mtrr: Assume SYS_CFG[Tom2ForceMemTypeWB] exists on all future AMD CPUs
  x86, k8: Rename k8.[ch] to amd_nb.[ch] and CONFIG_K8_NB to CONFIG_AMD_NB
  x86, k8-gart: Decouple handling of garts and northbridges
  x86, cacheinfo: Fix dependency of AMD L3 CID
  x86, kvm: add new AMD SVM feature bits
  x86, cpu: Fix allowed CPUID bits for KVM guests
  x86, cpu: Update AMD CPUID feature bits
  x86, cpu: Fix renamed, not-yet-shipping AMD CPUID feature bit
  x86, AMD: Remove needless CPU family check (for L3 cache info)
  x86, tsc: Remove CPU frequency calibration on AMD

  Linus Torvalds

  2010-10-22 04:01:08 +0800  

25 Sep, 2010

1 commit

• a46590533   x86/hwmon: fix initialization of coretemp ... Browse Code »

  43

  Using cpuid_eax() to determine feature availability on other than
  the current CPU is invalid. And feature availability should also be
  checked in the hotplug code path.

  Signed-off-by: Jan Beulich
  Cc: Rudolf Marek
  Cc: Fenghua Yu
  Signed-off-by: Guenter Roeck

  Jan Beulich

  2010-09-25 02:44:19 +0800  

09 Sep, 2010

1 commit

• aeb9c7d61   x86, kvm: add new AMD SVM feature bits ... Browse Code »

  The recently updated CPUID specification names new SVM feature bits.
  Add them to the list of reported features.

  Signed-off-by: Andre Przywara
  LKML-Reference:
  Signed-off-by: H. Peter Anvin

  Andre Przywara

  2010-09-09 04:34:15 +0800  

31 Jul, 2010

1 commit

• 9792db617   x86, cpu: Package Level Thermal Control, Power Limit Notification definitions ... Browse Code »

  Add package level thermal and power limit feature support.

  The two MSRs and features are new starting with Intel's Sandy Bridge processor.

  Please check Intel 64 and IA-32 Architectures SDMV Vol 3A 14.5.6 Power Limit
  Notification and 14.6 Package Level Thermal Management.

  This patch also fixes a bug which defines reverse THERM_INT_LOW_ENABLE bit and
  THERM_INT_HIGH_ENABLE bit.

  [ hpa: fixed up against current tip:x86/cpu ]

  Signed-off-by: Fenghua Yu
  LKML-Reference:
  Reviewed-by: Len Brown
  Signed-off-by: H. Peter Anvin

  Fenghua Yu

  2010-07-31 07:15:32 +0800  

20 Jul, 2010

1 commit

• 2decb194e   x86, cpu: Split addon_cpuid_features.c ... Browse Code »

  addon_cpuid_features.c contains exactly two almost completely
  unrelated functions, plus has a long and very generic name. Split it
  into two files, scattered.c for the scattered feature flags, and
  topology.c for the topology information.

  Signed-off-by: H. Peter Anvin
  LKML-Reference:

  H. Peter Anvin

  2010-07-20 10:02:41 +0800