01 Nov, 2019
1 commit
11 Apr, 2019
1 commit
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Add the missing complete operations for dma_completion to fix the
problem of blocking at the wait_for_completion_interruptible()
function in some situations.Signed-off-by: Clark Wang
(cherry picked from commit a19a00c51df5c3ead4d64ea3136f5bce60b2e6af)
21 Mar, 2019
1 commit
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Fixes: 944c01a889d9 ("spi: lpspi: enable runtime pm for lpspi")
Signed-off-by: kbuild test robot
Signed-off-by: Mark Brown
15 Mar, 2019
1 commit
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Related issues have been fixed by (e0e542aeb46a MLK-20060-1 spi: lpspi:
fix wrong transmission when don't use CONT). However, the delay between
sending and receiving in slave mode. This causes the value of
FSR_RXCOUNT cannot reflect whether there is still data not sent timely.
So do this judgement by FSR_TXCOUNT.Signed-off-by: Clark Wang
12 Feb, 2019
34 commits
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The spi_transfer *t will be used in one transfer whatever. If t is NULL,
there has no need to try sending data, so add an error return here.Signed-off-by: Clark Wang
Acked-by: Fugang Duan -
Add dma mode support for LPSPI. Any frame longer than half txfifosize will
be sent by dma mode.For now, there are some limits:
1. The maximum transfer speed in master mode depends on the slave device,
at least 40MHz(tested by spi-nor on 8qm-lpddr4-arm2 base board);
2. The maximum transfer speed in slave mode is 15MHz(imx7ulp),
22MHz(8qm/qxp).Signed-off-by: Clark Wang
Acked-by: Fugang Duan -
Use the default implementation of transfer_one_msg/chipselect/setup
functions in spi core to implement cs-gpio control.
Use fsl_lpspi_prepare_message to init the cs_gpio pin.Signed-off-by: Clark Wang
Acked-by: Fugang Duan -
Add a error info when set a speed which greater than half of per-clk of
spi module.The minimum SCK period is 2 cycles(CCR[SCKDIV]). So the maximum transfer
speed is half of spi per-clk.Signed-off-by: Clark Wang
Acked-by: Fugang Duan -
Add judgment on SR_MBF and FSR_RXCOUNT.
In PIO mode, if don't use CONT to keep cs selected in one transfer, the
transfer will go wrong. FCIE will be set after one frame transfer
finish. If use CONT, the frame refer to the whole data in one transfer.
If don't use CONT, the frame refer to one byte of whole data. This will
cause the transfer ending early.This patch add a register reading in isr function, it might lead to a
slight decrease in the max transmission speed in PIO mode.Signed-off-by: Clark Wang
Acked-by: Fugang Duan -
Add cs-gpio feature. Use fsl_lpspi_prepare_message() and
fsl_lpspi_unprepare_message() to enable and control cs line.
These two functions will be only called at the beginning and the ending
of a message transfer.Still can use the mode without cs-gpio. The two ways can refer to
fsl-imx8qm-lpddr4-arm2-lpspi.dts for setting the lpspi configration in
dts file.Signed-off-by: Clark Wang
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Add pio spi slave mode support for imx6ul which is based on the patch
cherry-pick from community(71abd29057cb17b6b9532421821dc443427399ed).Because the original imx6ul is bound to mx51 in the dts file.
However, in the slave mode, the patch in the community only adds two
functions mx53_ecspi_rx_slave/mx53_ecspi_tx_slave. Therefore, configure
mx51/6ul to use these two functions for data transmission and reception
in slave mode.Acked-by: Fugang Duan
Signed-off-by: Clark Wang -
Previously i.MX SPI controller only works in Master mode.
This patch adds support to i.MX51, i.MX53 and i.MX6 ECSPI
controller to work also in Slave mode.Currently SPI Slave mode support patch has the following limitations:
1. The stale data in RXFIFO will be dropped when the Slave does any new
transfer.
2. One transfer can be finished only after all transfer->len data been
transferred to master device
3. Slave device only accepts transfer->len data. Any data longer than this
from master device will be dropped. Any data shorter than this from
master will cause SPI to stuck due to mentioned HW limitation 2.
4. Only PIO transfer is supported in Slave mode.
5. Dynamic burst size adjust isn't supported in Slave mode.Following HW limitation applies:
1. ECSPI has a HW issue when works in Slave mode, after 64
words written to TXFIFO, even TXFIFO becomes empty,
ECSPI_TXDATA keeps shift out the last word data,
so we have to disable ECSPI when in slave mode after the
transfer completes
2. Due to Freescale errata ERR003775 "eCSPI: Burst completion by Chip
Select (SS) signal in Slave mode is not functional" burst size must
be set exactly to the size of the transfer. This limit SPI transaction
with maximum 2^12 bits. This errata affects i.MX53 and i.MX6 ECSPI
controllers.Signed-off-by: Jiada Wang
Signed-off-by: Mark Brown -
Use SR_TDF to judge if need send data, and SR_FCF to judge if
transmission end to replace the waiting after transmission end. This
waiting has no actual meaning, for the real end will set the FCF
flag.Resolved an issue that could cause a transmission timeout when
transferring large amounts of data.After making these changes, there is no need to use
fsl_lpspi_txfifo_empty(), so remove it.Signed-off-by: Xiaoning Wang
Reviewed-by: Fugang Duan -
Remove Reset operation in fsl_lpspi_config(). This RST may cause both CLK and
CS pins go from high to low level under cs-gpio mode.
Add fsl_lpspi_reset() function after one message transfer to clear all
flags in use.Signed-off-by: Xiaoning Wang
Reviewed-by: Fugang Duan -
enable the runtime pm for lpspi module
BuildInfo:
- U-Boot 2018.03-imx_4.14.ySigned-off-by: Han Xu
Reviewed-by: Frank Li
Signed-off-by: Xiaoning Wang -
Add both ipg and per clock for lpspi to support i.MX8QM/QXP boards.
Signed-off-by: Xiaoning Wang
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Add new setup_wml() for i.mx6ul, otherwise, kernel crash triggered
since no such function on i.mx6ul.This issue is brought by
commit 85c124bbc1c4 ("MLK-18983-1: spi: imx: move wml setting to
later than setup_transfer").Signed-off-by: Robin Gong
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Correct wml as the last rx sg length instead of the whole transfer
length.Signed-off-by: Robin Gong
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Current dynamic burst lengt
h is based on the whole transfer length,
that's ok if there is only one sg, but not correct in case multi sgs
in one transfer,because the tail data should based on the last sg
length instead of the whole transfer length. Move wml setting for DMA
to the later place, thus, the next patch could get the right last sg
length for wml setting. This patch is a preparation one, no any
function change involved.Signed-off-by: Robin Gong
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Add SPI slave mode for imx7ulp.
Need use imx7ulp-evk-spi-slave.dtb to boot.
Slave has to send the message which is same as the length of message
master sent.Wire connection:
GND, SCK, MISO(to MISO of slave), MOSI(to MOSI of slave), SCSSigned-off-by: Xiaoning Wang
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fsl,spi-num-chipselects may not assigned in DT, don't return EINVALID in
this case.Signed-off-by: Han Xu
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Below description copied from RM:
"RX_THRESHOLD. This field defines the FIFO threshold that triggers
a RX DMA/INT request.A RX DMA/INT request is issued when the number
of data entries in the RXFIFO is greater than RX_THRESHOLD."
Then, the RX_THRESHOLD of ECSPIx_DMAREG should be set as 'wml-1',
otherwise, the last 'wml' number of data in rxfifo will never be pulled
out.Signed-off-by: Robin Gong
Reviewed-by: Han Xu -
Upstreaming code already support dynamically adjust watermark with
the transfer count, so in case 'wml=1', tx wml will be set to 0
after divided by 2, which cause tx dma never start.Actually, don't
need promise tx_wml=rx_wml/2 any more, because the max wml for tx/rx
is half of fifo size and sdma script have already check the data count
in RXFIFO, if more than half of rxfifo data remain in rxfifo, tx dma
will never start transfer next 'watermark'(the max count maybe the half
of fifo size) data until the data in rxfifo less than half of rxfifo.
So never any data loss happen. Remove 'wml/2'.Signed-off-by: Robin Gong
Reviewed-by: Han Xu -
This patch revert "MLK-17619: spi: ecspi: request gpio resources
before setting the value", because spi_imx_setup() will be called
several times accroding to the spc definition. So remove the gpio
request operation out from spi_imx_setup(), and back to probe(),
and move up the location, just incase set the cs gpio value before
request gpio resources.This reverts commit aba5f6342002ffe1f13a71dbddf30ec15ee1edba.
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gpio controller ignored all values were set before request resources,
move the devm_gpio_request to spi_imx_setup to fix the issue.Signed-off-by: Han Xu
Suggested-and-reviewed-by: Fugang Duan -
The spi_imx IP block is also present on i.MX8M, so allow it
to be built for this platform.Signed-off-by: Fabio Estevam
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Use PIO if transfer length is smaller than wml instead of DMA mode.
That means some spi-nor driver such as m25p32 may setup one small size
transfer to probe device id from external spi-nor devicee by PIO mode
instead of DMA which can avoid checking sdma firmware ready during spi-nor
driver probe.Signed-off-by: Robin Gong
Acked-by: Fugang Duan -
1. Fix code error of changing lpspi clock polarity.
2. Set one SPI clock period for DBT parameter.
Signed-off-by: Gao Pan
Reviewed-by: Han Xu -
enable the lpspi config for arm64 in Kconfig
BuildInfo: SCFW 9e9f6ec6, IMX-MKIMAGE 0, ATF 0
Reviewed-by: Pan Gao
Signed-off-by: Han Xu -
Add imx6ul device type in spi driver to enable the ERR008517 workaround
or not by dts easily.Signed-off-by: Robin Gong
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To workaroud the TKT238285, the safe way is use XCH mode in SDMA
script to simulate as PIO mode which never report such issue. Meanwhile,
set tx threashold as 0. But this workaroud will bring performance impacted,
below performance data is collected by 'dd' with SPI-NOR flash on i.mx6dl
sabresd board:mode write data read data
--PIO 194KB/s 644KB/s
--DMA normal
(SMC, tx_thresh=32) 222KB/s 1.4MB/s
--DMA(XCH, tx_thresh=0) 210KB/s 1.0MB/sSigned-off-by: Robin Gong
(cherry picked from commit 01be65fa5617aa192307ca38b6fc6128f3f0c3f7)
(cherry picked from commit 646a751a4d1d0e227a762b461d9b8f92605c26b1)
(cherry picked from commit b334993950b24ced30fcfc70c126b65bf4cb4cff)Conflicts:
drivers/spi/spi-imx.c -
On i.MX7ULP sillicon, system suspend go through VLLS mode that gate
off pinctrl and modules power, then all registers are reset to HW
default value. To support the feature, driver needs to recover all
registers status.Signed-off-by: Gao Pan
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SPI IOMUX is changed into reset state in LPSR mode. As a result,
spi can't work again.This patch sets spi IOMUX to default state.
(cherry-picked from commit 2c8603c31831bb355f6be5b015377fb8fbd89844)
Signed-off-by: Gao Pan
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This is done in preperation for low power mode. Convert all clk_enable
to clk_prepare_enable and clk_disable to clk_disable_unprepare. Make sure
PLL3 power down when entering low power mode.Signed-off-by: Bai Ping
(cherry picked from commit 1808b31fdae576e775159a05cde9b45e404bb6e2) -
There is official workaound for TKT238285, so remove the limitation
for i.mx6dl.Signed-off-by: Robin Gong
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We set both wartermark of txfifo and rxfifo 32 as half of fifo length 64.
That will cause easy rxfifo overflow:
If there is 31 bytes in rxfifo, rx script will wait the next dma request
(the 32th data come into the rxfifo) and schedule out to tx script. Once
tx script start to run, the rx script need to wait tx script finish even
if its priority higher than tx. Meanwhile, spi slave device may input
data continous, plus the rx data which triggered by new tx script(32 bytes).
That will quickly consume whole 64 bytes fifo, so we keep 16bytes availbale
even in the worst case new tx script triggered during two rx transfer. That
may slow down tx slightly, but better than overflow and RX DMA timeout.Signed-off-by: Robin Gong
(cherry picked from commit 16043ad0ad96aa04a90614e473aa17980af4b8af)
(cherry picked from commit 819efee83b7b1f47685dca6fad6bbe17f1c42092)
(cherry picked from commit 5c4c7d05bbba0ea2b26ef2f3ae83119d5eada235) -
This reverts commit 0cc6feb5c4b5e6e1d1fa98f97b28ba79d6b5cb1b.
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This reverts commit 089651ef038eb4af77b0847615f909d2edce1bc2.
10 Jan, 2019
2 commits
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commit 29bdedfd9cf40e59456110ca417a8cb672ac9b92 upstream.
Commit e82b0b382845 ("spi: bcm2835: Fix race on DMA termination") broke
the build with COMPILE_TEST=y on arches whose cmpxchg() requires 32-bit
operands (xtensa, older arm ISAs).Fix by changing the dma_pending flag's type from bool to unsigned int.
Fixes: e82b0b382845 ("spi: bcm2835: Fix race on DMA termination")
Signed-off-by: Lukas Wunner
Signed-off-by: Mark Brown
Cc: Frank Pavlic
Cc: Martin Sperl
Cc: Noralf Trønnes
Cc: Sudip Mukherjee
Signed-off-by: Greg Kroah-Hartman -
commit 56c1723426d3cfd4723bfbfce531d7b38bae6266 upstream.
The IRQ handler bcm2835_spi_interrupt() first reads as much as possible
from the RX FIFO, then writes as much as possible to the TX FIFO.
Afterwards it decides whether the transfer is finished by checking if
the TX FIFO is empty.If very few bytes were written to the TX FIFO, they may already have
been transmitted by the time the FIFO's emptiness is checked. As a
result, the transfer will be declared finished and the chip will be
reset without reading the corresponding received bytes from the RX FIFO.The odds of this happening increase with a high clock frequency (such
that the TX FIFO drains quickly) and either passing "threadirqs" on the
command line or enabling CONFIG_PREEMPT_RT_BASE (such that the IRQ
handler may be preempted between filling the TX FIFO and checking its
emptiness).Fix by instead checking whether rx_len has reached zero, which means
that the transfer has been received in full. This is also more
efficient as it avoids one bus read access per interrupt. Note that
bcm2835_spi_transfer_one_poll() likewise uses rx_len to determine
whether the transfer has finished.Signed-off-by: Lukas Wunner
Fixes: e34ff011c70e ("spi: bcm2835: move to the transfer_one driver model")
Cc: stable@vger.kernel.org # v4.1+
Cc: Mathias Duckeck
Cc: Frank Pavlic
Cc: Martin Sperl
Cc: Noralf Trønnes
Signed-off-by: Mark Brown
Signed-off-by: Greg Kroah-Hartman
