18 Dec, 2020
1 commit
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* origin/clock/s32: (9 commits)
LF-632 clk: s32v234: Fix "enetpll_dfs3" position in sdhc_sels
clk: s32v234: Enable FlexCAN clock
clk: s32v234: Add definitions for CAN clocks
clk: s32v234: Initial enet clk support
clk: s32v234: Add dfs clk
...
14 Dec, 2020
35 commits
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Define macros which will indicate the clock signals obtained after
auxiliary clock 6 source selection and division (CAN_CLK) respectively.Signed-off-by: Stoica Cosmin-Stefan
Signed-off-by: Stefan-Gabriel Mirea -
Add ethernet clocks and dependencies (sys_pll, arm_pll)
Based on ALB v4.19.31_bsp23.0_rc2
Signed-off-by: Leonard Crestez
Reviewed-by: Fugang Duan -
Enable the clocks needed for uSDHC support on Treerunner.
Signed-off-by: Stoica Cosmin-Stefan
Signed-off-by: Larisa Grigore
Signed-off-by: Stefan-Gabriel Mirea -
Enable the clocks needed for LINFlexD UART support on Treerunner and make
use of them in the LINFlexD driver.Signed-off-by: Stoica Cosmin-Stefan
Signed-off-by: Adrian.Nitu
Signed-off-by: Larisa Grigore
Signed-off-by: Iustin Dumitrescu
Signed-off-by: Stefan-Gabriel Mirea
Signed-off-by: Leonard Crestez -
Add DT bindings documentation for the upcoming S32V234 clk driver. Add
s32v234-clock.h header, which is referred in MC_CGM documentation.Signed-off-by: Stoica Cosmin-Stefan
Signed-off-by: Stefan-Gabriel Mirea -
Remove all MLB clock setting for imx8qm/qxp.
Reviewed-by: Fugang Duan
Signed-off-by: Clark Wang -
There is hardware issue: TKT0535653
SDMA3 can't work without setting AUDIOMIX_CLKEN0[SDMA2] (bit-26) to 1The workaround is:
As the reset state of AUDIOMIX_CLKEN0[SDMA2] is enabled,
we just need to keep it on as reset state, don't touch it
in kernel, then every thing is same as before, if we register
the clock in clk-audiomix, then kernel will try to disable
it in idle.Signed-off-by: Shengjiu Wang
Reviewed-by: Daniel Baluta
Reviewed-by: Jacky Bai
Reviewed-by: Robin Gong -
These IDs will be used by the platform clock controller driver
to register the clocks even if they are not populated on
a specific board. And that's okay, because it will allow the
driver to remain unchanged, the only thing changing will be the
dtb between boards which will override the properties of each
specific SAI MCLK devicetree node as necessary, if the board
has populated the any of the SAIx_MCLK pins with an input clock.Signed-off-by: Abel Vesa
Reviewed-by: Shengjiu Wang -
These will be used by the imx8mp for blk-ctrl driver.
Signed-off-by: Abel Vesa
Reviewed-by: Dong Aisheng
Tested-by: Daniel Baluta -
These will be used by the imx8mp for blk-ctrl driver.
Signed-off-by: Abel Vesa
Reviewed-by: Dong Aisheng
Tested-by: Daniel Baluta -
All these IDs are for one single HW gate (CCGR101) that is shared
between these root clocks.Signed-off-by: Abel Vesa
Reviewed-by: Dong Aisheng
Tested-by: Daniel Baluta -
In the reference manual the actual name is Audio BLK_CTRL.
Lets make it more obvious here by renaming from audiomix to audio_blk_ctrl.Signed-off-by: Abel Vesa
Reviewed-by: Dong Aisheng
Tested-by: Daniel Baluta -
This patch adds "media_ldb_root_clk" clock for
the LDB in the MEDIAMIX subsystem.Reviewed-by: Sandor Yu
Signed-off-by: Liu Ying
[ Aisheng: update clock id ]
Signed-off-by: Dong Aisheng -
This patch adds DISP2 pixel clock for the second instance of LCDIFv3
in the MEDIAMIX subsystem.Reviewed-by: Sandor Yu
Signed-off-by: Liu Ying
[ Aisheng: change to imx8m_clk_hw_composite_bus and update clock id ]
Signed-off-by: Dong Aisheng -
This clock is a high precision clock on imx8mq-evk board that will be used by
HDMI phy.Signed-off-by: Laurentiu Palcu
[ Aisheng: update clk id to new value due to upstream change ]
Signed-off-by: Dong Aisheng -
add audio acm clocks
Signed-off-by: Shengjiu Wang
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This patch forwards some IPUv3 and LDB clock changes from imx_4.19.y kernel,
as needed to enable internal IPUv3 fb and LVDS displays.Signed-off-by: Liu Ying
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add pxp ipg/axi clock on imx7d
Signed-off-by: Robby Cai
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remove legacy lpcg clock binding support to avoid confusing
Signed-off-by: Dong Aisheng
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remove legacy scu clock binding support to avoid confusing
Signed-off-by: Dong Aisheng
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The ENET RMII 50M SCU Ref clock was wrongly put in LPCG clock ID
definition which may overwrite the SCU clock IDs.
Fix it by move it into the correct place.Signed-off-by: Dong Aisheng
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Add enet0/1 RMII mode reference clock support.
Signed-off-by: Fugang Duan
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Correct enet clock tree according to ADD documentation.
Signed-off-by: Fugang Duan
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Add clocks for parallel port capture interface of IMX8QXP.
Because digital pll for parallel interface is on by default, and
not provide enable/disable function by scu, so add the related ops
for this kind of clocks.Signed-off-by: Guoniu.zhou
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Signed-off-by: Dong Aisheng
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Signed-off-by: Dong Aisheng
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Signed-off-by: Dong Aisheng
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Signed-off-by: Dong Aisheng
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add audio clocks
Signed-off-by: Shengjiu Wang
[ Aisheng: change to module format in Makefile ]
Signed-off-by: Dong Aisheng -
For both USB2 controller and USB PHY.
Signed-off-by: Peter Chen
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Add MIPI CSI clocks for image subsystem of IMX8QXP
Signed-off-by: Guoniu.zhou
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Add LPCG clocks for ISI of image subsystem
Signed-off-by: Guoniu.zhou
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Add the lpcg clocks for hsio.
Signed-off-by: Richard Zhu
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Add scu clocks and lpcg clocks for i2c which is in cm40 subsystem.
Signed-off-by: Joakim Zhang
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add CONN SS PLL clock IDs
Cc: Stephen Boyd
Cc: Shawn Guo
Cc: Sascha Hauer
Cc: Fabio Estevam
Cc: Michael Turquette
Signed-off-by: Dong Aisheng
25 Oct, 2020
1 commit
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Pull ARM Devicetree updates from Olof Johansson:
"As usual, most of the changes are to devicetrees.Besides smaller fixes, some refactorings and cleanups, some of the new
platforms and chips (or significant features) supported are below:Broadcom boards:
- Cisco Meraki MR32 (BCM53016-based)
- BCM2711 (RPi4) display pipeline supportActions Semi boards:
- Caninos Loucos Labrador SBC (S500-based)
- RoseapplePi SBC (S500-based)Allwinner SoCs/boards:
- A100 SoC with Perf1 board
- Mali, DMA, Cetrus and IR support for R40 SoCAmlogic boards:
- Libretch S905x CC V2 board
- Hardkernel ODROID-N2+ boardAspeed boards/platforms:
- Wistron Mowgli (AST2500-based, Power9 OpenPower server)
- Facebook Wedge400 (AST2500-based, ToR switch)Hisilicon SoC:
- SD5203 SoCNvidia boards:
- Tegra234 VDK, for pre-silicon Orin SoCNXP i.MX boards:
- Librem 5 phone
- i.MX8MM DDR4 EVK
- Variscite VAR-SOM-MX8MN SoM
- Symphony board
- Tolino Shine 2 HD
- TQMa6 SoM
- Y Soft IOTA OrionRockchip boards:
- NanoPi R2S board
- A95X-Z2 board
- more Rock-Pi4 variantsSTM32 boards:
- Odyssey SOM board (STM32MP157CAC-based)
- DH DRC02 boardToshiba SoCs/boards:
- Visconti SoC and TPMV7708 board"* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (638 commits)
ARM: dts: nspire: Fix SP804 users
arm64: dts: lg: Fix SP804 users
arm64: dts: lg: Fix SP805 clocks
ARM: mstar: Fix up the fallout from moving the dts/dtsi files
ARM: mstar: Add mstar prefix to all of the dtsi/dts files
ARM: mstar: Add interrupt to pm_uart
ARM: mstar: Add interrupt controller to base dtsi
ARM: dts: meson8: remove two invalid interrupt lines from the GPU node
arm64: dts: ti: k3-j7200-common-proc-board: Add USB support
arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function
arm64: dts: ti: k3-j7200-main: Add USB controller
arm64: dts: ti: k3-j7200-main.dtsi: Add USB to SERDES lane MUX
arm64: dts: ti: k3-j7200-main: Add SERDES lane control mux
dt-bindings: ti-serdes-mux: Add defines for J7200 SoC
ARM: dts: hisilicon: add SD5203 dts
ARM: dts: hisilicon: fix the system controller compatible nodes
arm64: dts: zynqmp: Fix leds subnode name for zcu100/ultra96 v1
arm64: dts: zynqmp: Remove undocumented u-boot properties
arm64: dts: zynqmp: Remove additional compatible string for i2c IPs
arm64: dts: zynqmp: Rename buses to be align with simple-bus yaml
...
21 Oct, 2020
3 commits
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…'clk-prima2' and 'clk-bcm' into clk-next
- Support qcom SM8150/SM8250 video and display clks
- Change how qcom's display port clks work* clk-ingenic:
clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate
clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT
clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL
clk: ingenic: Use readl_poll_timeout instead of custom loop
clk: ingenic: Use to_clk_info() macro for all clocks* clk-at91:
clk: at91: sam9x60: support only two programmable clocks
clk: at91: clk-sam9x60-pll: remove unused variable
clk: at91: clk-main: update key before writing AT91_CKGR_MOR
clk: at91: remove the checking of parent_name* clk-kconfig:
clk: Restrict CLK_HSDK to ARC_SOC_HSDK* clk-imx:
clk: imx8mq: Fix usdhc parents order
clk: imx: imx21: Remove clock driver
clk: imx: gate2: Fix a few typos
clk: imx: Fix and update kerneldoc
clk: imx: fix i.MX7D peripheral clk mux flags
clk: imx: fix composite peripheral flags
clk: imx: Correct the memrepair clock on imx8mp
clk: imx: Correct the root clk of media ldb on imx8mp
clk: imx: vf610: Add CRC clock
clk: imx: Explicitly include bits.h
clk: imx8qxp: Support building i.MX8QXP clock driver as module
clk: imx8m: Support module build
clk: imx: Add clock configuration for ARMv7 platforms
clk: imx: Support building i.MX common clock driver as module
clk: composite: Export clk_hw_register_composite()
clk: imx6sl: Use BIT(x) to avoid shifting signed 32-bit value by 31 bits* clk-qcom:
clk: qcom: gdsc: Keep RETAIN_FF bit set if gdsc is already on
clk: qcom: Add display clock controller driver for SM8150 and SM8250
dt-bindings: clock: add QCOM SM8150 and SM8250 display clock bindings
clk: qcom: add video clock controller driver for SM8250
clk: qcom: add video clock controller driver for SM8150
dt-bindings: clock: add SM8250 QCOM video clock bindings
dt-bindings: clock: add SM8150 QCOM video clock bindings
dt-bindings: clock: combine qcom,sdm845-videocc and qcom,sc7180-videocc
clk: qcom: gcc-msm8994: Add missing clocks, resets and GDSCs
clk/qcom: fix spelling typo
clk: qcom: gcc-sdm660: Fix wrong parent_map
clk: qcom: dispcc: Update DP clk ops for phy design
clk: qcom: gcc-msm8939: remove defined but not used variables
clk: qcom: ipq8074: make pcie0_rchng_clk_src static* clk-prima2:
clk: clk-prima2: fix return value check in prima2_clk_init()* clk-bcm:
clk: bcm2835: add missing release if devm_clk_hw_register fails
clk: bcm: rpi: Add register to control pixel bvb clk -
…diatek' into clk-next
- Small non-critical fixes for TI clk driver
- Support Mediatek MT8167 clks* clk-simplify:
clk: mediatek: fix platform_no_drv_owner.cocci warnings
clk: mediatek: mt7629: simplify the return expression of mtk_infrasys_init
clk: mediatek: mt6797: simplify the return expression of mtk_infrasys_init* clk-ti:
clk: ti: dra7: add missing clkctrl register for SHA2 instance
clk: ti: clockdomain: fix static checker warning
clk: ti: autoidle: add checks against NULL pointer reference
clk: keystone: sci-clk: add 10% slack to set_rate
clk: keystone: sci-clk: cache results of last query rate operation
clk: keystone: sci-clk: fix parsing assigned-clock data during probe* clk-tegra:
clk: tegra: Drop !provider check in tegra210_clk_emc_set_rate()* clk-rockchip:
clk: rockchip: Initialize hw to error to avoid undefined behavior
clk: rockchip: rk3399: Support module build
clk: rockchip: fix the clk config to support module build
clk: rockchip: Export some clock common APIs for module drivers
clk: rockchip: Export rockchip_register_softrst()
clk: rockchip: Export rockchip_clk_register_ddrclk()
clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls
clk: rockchip: rk3308: drop unused mux_timer_src_p* clk-mediatek:
clk: mediatek: Add MT8167 clock support
dt-bindings: clock: mediatek: add bindings for MT8167 clocks
clk: mediatek: add UART0 clock support -
…k-doc' and 'clk-unused' into clk-next
- Remove various unused variables in clk drivers
* clk-renesas:
clk: renesas: rcar-gen3: Update description for RZ/G2
clk: renesas: cpg-mssr: Add support for R-Car V3U
clk: renesas: cpg-mssr: Add register pointers into struct cpg_mssr_priv
clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag
dt-bindings: clock: renesas,cpg-mssr: Document r8a779a0
dt-bindings: clock: Add r8a779a0 CPG Core Clock Definitions
dt-bindings: power: Add r8a779a0 SYSC power domain definitions
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
clk: renesas: r8a7742: Add clk entry for VSPR* clk-amlogic:
clk: meson: make shipped controller configurable
clk: meson: g12a: mark fclk_div2 as critical
clk: meson: axg-audio: fix g12a tdmout sclk inverter
clk: meson: axg-audio: separate axg and g12a regmap tables
clk: meson: add sclk-ws driver* clk-allwinner:
clk: sunxi-ng: sun8i: r40: Use sigma delta modulation for audio PLL
clk: sunxi-ng: add support for the Allwinner A100 CCU
dt-bindings: clk: sunxi-ccu: add compatible string for A100 CCU and R-CCU* clk-samsung:
clk: s2mps11: initialize driver via module_platform_driver
clk: samsung: Use cached clk_hws instead of __clk_lookup() calls
clk: samsung: exynos5420/5250: Add IDs to the CPU parent clk definitions
clk: samsung: Add clk ID definitions for the CPU parent clocks
clk: samsung: exynos5420: Avoid __clk_lookup() calls when enabling clocks
clk: samsung: exynos5420: Add definition of clock ID for mout_sw_aclk_g3d
clk: samsung: Keep top BPLL mux on Exynos542x enabled* clk-doc:
clk: davinci: add missing kerneldoc
clk: fixed: add missing kerneldoc* clk-unused:
clk: socfpga: agilex: Remove unused variable 'cntr_mux'
clk: si5341: drop unused 'err' variable
clk: mmp: pxa1928: drop unused 'clk' variable
clk: at91: drop unused at91sam9g45_pcr_layout
