08 Jun, 2017
40 commits
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This reverts commit 2c01452f4d7c0f65553b365adc27a1b7b6ba8644.
Besides, add other SoC request high bus freq. This is because
only imx6qdl do not implement low bus idle, so imx6qdl can work
well under low power mode without request high bus freq which
also can save power. For other SoC, need to request high bus
freq when usdhc is active.Also can refer to commit 312979d1fcbd.
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The timing settings for 100MHz are almost the same as the ones for
400MHz except for the MMDCx_MISC[RALAT] parameter which needs to be
set to 2 cycles.For the 100MHz case the restoration of the mmdc setting should be performed
in 2 steps: restore the mmdc setting and then overwrite the RALAT setting
for 2 cycles.A decision code within the "mmdc_clk_lower_equal_100MHz" macro is added
to go to the "equal to 100MHz" or to the "lower to 100MHz" caseSigned-off-by: Juan Gutierrez
Signed-off-by: Alejandro Lozano -
Setting the Read Additional Latency (RALAT) to 2 cycles,
MMDCx_MDMISC[RALAT] = 2, is needed for 24MHz operation point.Currently this is set within the "set_timings_below_100MHz_operation"
macro, which is use for the 24MHz case.In order to provide a generic way for setting RALAT=2 the code
is wrapped in this new macro: "set_mmdc_misc_ralat_2_cycles", so
other set points (besides the below 100MHz case) can reuse this code.As an example, for 100Mhz operation the RALAT should be set to 2 cycles,
however, the rest of the MMDCFG parameter are not the same as in the
"below_100MHz" case. So, this macro can be reused for its RALAT part.Signed-off-by: Juan Gutierrez
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Two macros are renamed:
1) set_timings_above_100MHz_operation as restore_mmdc_settings_info
2) mmdc_clk_lower_100MHz as mmdc_clk_lower_equal_100MHzFor (1) the operation is generic to several cases and not just related
(at least on a semantic way) with the operations "above" 100MHzRenamed as restore_mmdc_settings_info the macro can be reused for the
other cases like equal to 100MHz and possibly other intermediate
operation points.For (2), the macro is renamed as mmdc_clk_lower_equal_100MHz to reflect
that this macro handles both the "lower than 100 MHz" case and the
"equal to 100MHz" case.Signed-off-by: Juan Gutierrez
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system can't detect SD card due to wrong gpio polarity.
Signed-off-by: Dong Aisheng
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The new parameter description is:
gpr = ;Signed-off-by: Shengjiu Wang
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There is hard code for gpr address in machine driver, imx-wm8960
and imx-wm8958, when the sai interface changed to sai1 or sai3,
there will be issue, so remove the hard code, use the property
from the device tree.Signed-off-by: Shengjiu Wang
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When MMDC runs at a low frequency, it is not recommended to
perform "force measurement", the MMDC measure unit may return
a wrong measurement value when running below 100MHz.Additionally, the double MU count operations should be only done
when changing the MMDC frequency from 400MHz to a low
frequency(100MHz or 24MHz). Otherwise, the MU count may overflow
and lead to system hang issue.Signed-off-by: Bai Ping
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Add low power idle support on i.MX6SLL.
Signed-off-by: Bai Ping
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Add bufreq driver support on i.MX6SLL. For i.MX6SLL,
it only support LPDDR2 and LPDDR3. the DDR clock change
flow is same on these two type of DDR.Signed-off-by: Bai Ping
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Add busfreq device node for i.MX6SLL.
Signed-off-by: Bai Ping
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According to datasheet Rev.B,06/2016 of i.MX6SLL. It has below
setpoints support:
996MHz 1.2V
792MHz 1.15V
396MHz 1.05V
198MHz 0.95V
We add a 25mV margin to cover the IR drop and board tolerance.Signed-off-by: Bai Ping
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Increase the AXI and AHB clock rate on i.MX6SLL according to
the RM to improve the system bus performance.Signed-off-by: Bai Ping
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For mxs PHY, if there is a vbus but the bus is not enumerated,
force the dp/dm as SE0 from the consider side. If not, there
is possible USB wakeup due to unstable dp/dm, since there is
possible no pull on dp/dm, eg, there is a USB charger on the
port. Note, the vbus event is only occurred at device mode,
and sent by udc driver.Signed-off-by: Peter Chen
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Add USB PHY event for below situation:
- vbus connect
- vbus disconnect
- gadget driver is enumeratedUSB PHY driver can get the last event after above situation
occurs.Signed-off-by: Peter Chen
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Add DCP and RNG node in imx6sll.dtsi to enable them.
Signed-off-by: ye li
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Add i.MX6SLL EVK board dts file.
Signed-off-by: Bai Ping
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For i.MX6SLL LPDDR2 and LPDDR3 ARM2 board, they share the same
board design but using different DDR chip. So we can reuse the
LPDDR3 ARM2 board dts on LPDDR2 ARM2 board.Signed-off-by: Bai Ping
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Fix coverity CID 17624 uninitialized scalar variable
The 'fb_fmt' variable may be used before uninitialized
So initialize it at the begining.Signed-off-by: Guoniu.Zhou
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ECSPI1_SCLK pin is shared by LCD power enable and SPI1 SCLK.
To use ecspi, need to disable lcdif function.Signed-off-by: Robby Cai
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Add lcdif data/ctrl pin and power-enable pin setting
Add backlight/pwm setting
disable ecspi1 since ECSPI1_SCLK pin is also used as LCD power enable,
and add another dts file for ecspi1.Signed-off-by: Robby Cai
Signed-off-by: Fancy Fang -
since there's pin conflict between camera and epdc on this board,
we add a new dts file for csi/camera function.Signed-off-by: Robby Cai
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correct the base address for imx6sll CSI
Signed-off-by: Robby Cai
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enabled the wm8962 and spdif out.
There is pin conflict between spdif and usdhc2. So add
dedicate spdif dts.Signed-off-by: Shengjiu Wang
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add extern audio clock in imx6sll clock tree
Signed-off-by: Shengjiu Wang
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The calculation "runtime->status->hw_ptr * (runtime->frame_bits / 8)" may
exceed the integer scope, then appl_bytes is no correct.
This patch is to fix this issue.Signed-off-by: Shengjiu Wang
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correct the clock name for pxp and enable pxp
Signed-off-by: Robby Cai
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Add e-ink display PMIC setting, and add pin setting for epdc and the pmic.
Signed-off-by: Robby Cai
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At some boards, it has no ethernet support. As an alternative, we can use
USB Ethernet card to support NFS (u-boot supports it too). It supports
AXIS cards which are used most frequently.This commit is the similar with below mainline commit:
https://git.kernel.org/cgit/linux/kernel/git/peter.chen/usb.git/commit/
?h=peter-usb-dev&id=277ad756ead72845796c4f5430dd345301dc460bSigned-off-by: Peter Chen
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USBOTG1 is for dual-role, USBOTG2 is host-only due to pin conflict with EPDC.
Signed-off-by: Peter Chen
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The imx6sll is much like imx6ul, so add imx6ul compatible string for it.
Signed-off-by: Peter Chen
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correct VMINSYS_MASK and _CNFG_REGTEMP_MASK define for regmap
Signed-off-by: Robin Gong
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Charger interrupt can't be caught anymore after plug in DC 5V in/out dozens of
times, that caused by VBUS_I or CHG_I pending interrupt not cleared in time. The root
cause is VBUS_I and CHG_I will be triggered in very narrow window, and VBUS_I/CHG_I
act as the sub-interrupt of charger and share the same interrupt handler. Thus if CHG_I
interrupt status is coming while VBUS_I handler is running, CHG_I interrupt status will
never be cleared, since interrupt has been disabled in ISR. The unclear CHG_I interrupt
status make pf1550 never trigger next interrupt again. So clear all charger interrupt
status in ISR to workaround instead of ack for every sub-intterrupt.Signed-off-by: Robin Gong
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enable pf1550 charger driver.
Signed-off-by: Robin Gong
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remove useless DPMI interrupt in pf1550 charger.
Signed-off-by: Robin Gong
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remove usless DPMI interrupt.
Signed-off-by: Robin Gong
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That's pf1550's internal interrupt, usless for charger.
Signed-off-by: Robin Gong
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Do not probe if the device node is not correct in dts.
Signed-off-by: Robin Gong
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check OTP_SW2_DVS_ENB bit for the different voltage list while SW2
regulator registered.Signed-off-by: Robin Gong
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add otp read interface to let pf1550 regulator driver or other sub driver
to read out otp register.Signed-off-by: Robin Gong