27 Mar, 2014
1 commit
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Set the correct permissions of the fsl_disp_property sysfs entry.
Acked-by: Liu Ying
Signed-off-by: Julien Olivain
(cherry picked from commit 9db2d982c90b6edb3dfebe03a68f50f381bb99bb)
25 Mar, 2014
1 commit
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The HDMI IP in i.MX6DQ has a bug that it limits the dma period size within 8K.
Patch 'ENGR00300188-1 ASoC: imx-hdmi-dma: Double the buffer and period sizes'
doubled the period size which works great with Dual Lite but broke the HDMI
audio function on DQ. Thus fix it for 6DQ case.Acked-by: Wang Shengjiu
Signed-off-by: Nicolin Chen
21 Mar, 2014
1 commit
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The optimal resize ratio should be used if the downscaler is not needed. This
will fix a vertical line in the center for some scaling ratios.Signed-off-by: Oliver Brown
18 Mar, 2014
3 commits
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For HSIC operation at imx6sl, it needs host quirk too.
Signed-off-by: Peter Chen
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This flag is not only used for mxs phy's bug, but also
for speical routine for other imx host operations.Signed-off-by: Peter Chen
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This reverts commit 6cf1375d32049b7d852131d232ec97e76535a2e0
in order to avoid system hang access portsc without PHY clock.
See: http://marc.info/?l=linux-arm-kernel&m=139350618732108&w=2Signed-off-by: Peter Chen
17 Mar, 2014
8 commits
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The mipi csi2 code is ugly present in the capture pipeline setup/disable
routions with '#ifdef CONFIG_MXC_MIPI_CSI2/#endif' protected. Whenever
it finds mipi_csi2_info is not gotten correctly, it will return error to
callers. This breaks the normally routines in which mipi csi2 is not used
and mipi csi2 driver is disabled in its devicetree node(but with the
Kconfig CONFIG_MXC_MIPI_CSI2 defined). A real example is the capture
feature on the MX6 Sabreauto platforms. We have only parallel CSI input
on it and the mipi csi2 driver is disabled in its devicetree node but with
the Kconfig CONFIG_MXC_MIPI_CSI2 defined. So, a reasonable choice at present
is not to return error if mipi_csi2_info cannot be gotten, though we could
eventually re-organize the capture code for a better total solution in the
future.Signed-off-by: Liu Ying
(cherry picked from commit 8133b7fd26e8b068fa8ab9cd62eae090c76080be) -
xserver will read default video mode in command line by sysfs node
/sys/class/graphics/fb0/mode, but the sysfs node is not initialized
when system bootup without hdmi cable plugin
or frame buffer register in blank state.
Fixed:
- Remove unused previous_mode
- Add default_mode, initialize in disp_init function.
- Initialize fbi->mode in disp_init function and hdmi_setup function.Signed-off-by: Sandor Yu
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commit f8e1a3bb62eecf93a31a51c4dbe08a0214fa1d57 introduced an
annoying kernel log by changing a pure debug info to error level.
This patch reverts that change.Conflicts:
drivers/media/video/mxc/capture/mxc_v4l2_capture.c
Signed-off-by: Liu Ying
(cherry picked from commit b635fadfdff01d0f6112956ac903d80c62fd648b) -
commit f8e1a3bb62eecf93a31a51c4dbe08a0214fa1d57 added a hard
coding for csi_parma.mclk setting to 27MHz. The comment added by
that commit is totally wrong by telling that csi_param.mclk
would be a kind of 'pixel clock' set in 'csi_data_dest' register.
This patch removes the unnecessary mclk setting for csi_param.mclk
variable, since it is only valid for CSI test mode.Conflicts:
drivers/media/video/mxc/capture/mxc_v4l2_capture.c
Signed-off-by: Liu Ying
(cherry picked from commit bb5afd554c50b639f1e1b94481b24f35ae8c4dc5) -
This patch removes test mode clock setting in function
ipu_csi_init_interface(), since the setting is only
necessary for function _ipu_csi_set_test_generator().
This unnecessary setting is added wrongly by commit
f8e1a3bb62eecf93a31a51c4dbe08a0214fa1d57.Signed-off-by: Liu Ying
(cherry picked from commit 0f395a7aecfd2845df384c7a5a0045c86c3a2e20) -
We reversed CCIR code1/2 setting before, which may brings
captured frame quality issue(jaggy edge can be seen). This
patch revert that change.Signed-off-by: Liu Ying
(cherry picked from commit a4c2228f5428af02b9be87114d096340f9b58083) -
As the sabreauto CPU board schematics mentions, the MIPI connector
isn't mechanically compatible with Freescale MIPI display and camera
board, then we have no way to support MIPI features currently on
this platform. So, let's disable MIPI CSI.Signed-off-by: Liu Ying
(cherry picked from commit 453d409281228429270b9f294728e5cad1c63ee0) -
As the sabreauto CPU board schematics mentions, the MIPI connector
isn't mechanically compatible with Freescale MIPI display and camera
board, then we have only the parallel CSI video input that is supported
by the v4l2_cap_0 node. So, let's remove the orphan one - v4l2_cap_1.Signed-off-by: Liu Ying
(cherry picked from commit 1396bc28eac7e968e278a9ce36cdc7a44b0417bd)
14 Mar, 2014
2 commits
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The following error was reported.
-----------------------------------------------------------
root@imx6qdlsolo:~# /unit_tests/mxc_v4l2_capture.out -d /dev/video1 1.yuv
in_width = 176, in_height = 144
out_width = 176, out_height = 144
top = 0, left = 0
mipi csi2 can not receive sensor clk!
sensor chip is ov5640_mipi_camera
sensor supported frame size:
640x480
320x240
720x480
720x576
1280x720
1920x1080
2592x1944
176x144
1024x768
sensor frame format: UYVY
sensor frame format: UYVY
sensor frame format: UYVY
sensor frame format: UYVY
sensor frame format: UYVY
sensor frame format: UYVY
sensor frame format: UYVY
sensor frame format: UYVY
sensor frame format: UYVY
mipi csi2 can not receive sensor clk!
mxc_v4l2_s_param: vidioc_int_s_parm returned an error -1
VIDIOC_S_PARM failed
get format failed-----------------------------------------------------------
Root cause analysis:
It only happens when HDMI is not used/enabled. There is a clock named
video_27m which are needed by HDMI (as isfrclk's parent) and MIPI-CSI2 (as
cfg_clk's parent). MIPI-CSI2 driver is lack of enabling this clock before
start to work and only happen to work when HDMI driver enables this clock.Signed-off-by: Robby Cai
(cherry picked from commit a6bbc7d56f261ab84e04071487264c6a519df758) -
MIPI CSI2 depends on this clock to work.
This patch also updates the binding document.Signed-off-by: Robby Cai
(cherry picked from commit 67e7963f6f7ddb6c001bb34c6af71f2330fd0e3f)
12 Mar, 2014
1 commit
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After change the resolution, the blank state will be changed, the audio will
be triggered to start. which didn't care about the audio is running or not
before changing the resolution.
Add hdmi_abort_state for this special case.Signed-off-by: Shengjiu Wang
11 Mar, 2014
2 commits
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The offset reflects the current position of DMA access in the ALSA ring buffer.
So we should clear it before re-start DMA engine becasue the DMA access should
re-start its job from the 0 position. If we don't do this, the driver might get
a wrong idea about current position of DMA access. Thus fix it.Acked-by: Wang Shengjiu
Signed-off-by: Nicolin Chen
(cherry picked from commit 8f265543ffda0a19e3f469967a7d61d8b344f080) -
We found HDMI Audio has a performance issue when playback 8 channels 192KHz
files, CPU might lag its interrupt responsing while SDMA continues updating
HDMI internal AHB DMA's address and restarting AHB DMA, which resulted the
noise when AHB DMA access overlaps with the data copy procedures in this
driver.Thus we here double the buffer size and period size of HDMI Audio to chop
the CPU interrupt to its half in the same span of time so that we can keep
the data copy procedures safe and provent it from overlapping access with
AHB DMA.Acked-by: Wang Shengjiu
Signed-off-by: Nicolin Chen
(cherry picked from commit 04af1a351e016f52276ae002fd9f64b6b2962168)
07 Mar, 2014
1 commit
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LDO2p5 cannot be disabled in low power idle mode when the USB driver
enables VBUS wakeup. To identify when LDO2p5 can be disabled add a dummy
regulator that the USB driver will enable when VBUS wakeup is required.Signed-off-by: Ranjani Vaidyanathan
06 Mar, 2014
2 commits
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LDO2p5 cannot be disabled in low power idle mode when the USB driver
enables VBUS wakeup. To identify when LDO2p5 can be disabled add a dummy
regulator that the USB driver will enable when VBUS wakeup is required.This patch ensures that the low power idle code checks the status of the
dummy ldo2p5 regulator before disabling LDO2p5.Signed-off-by: Ranjani Vaidyanathan
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LDO2p5 cannot be disabled in low power idle mode when the USB driver
enables VBUS wakeup. To identify when LDO2p5 can be disabled add a dummy
regulator that the USB driver will enable when VBUS wakeup is required.
This patch adds the dummy regulator to the dts files.Signed-off-by: Ranjani Vaidyanathan
27 Feb, 2014
1 commit
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When dma zone memory used up, gckOS_AllocateNonPagedMemory() will try to
free non paged memory cache and allocate again. Such operation will cause
twice memory mutex request and cause gpu driver hang.The solution is free the memory mutex at first before trying to free non
paged memory cache.Date: Feb 27, 2014
Signed-off-by: Loren Huang
Acked-by: Shawn Guo
(cherry picked from commit 79ed8edd23f990f6c1429154c2ee773c83bfd72e)
21 Feb, 2014
1 commit
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Add hwrng support for i.MX6SL.
1. Add RNG driver. This driver originated as fsl-rngc.c. It
has been modified to support device tree. The name has been
changed since it supports both b and c variants of RNG.
2. Added clock and compatible info to the device tree data.
3. Added the entry in the options in the Kconfig for hwrng.Signed-off-by: Dan Douglass
20 Feb, 2014
2 commits
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When split mode deinterlacing is the ipu_calc_stripes_sizes() was failing due
to an unnecessary test. Added logic to use the maximal_stripe_width only if
the flag parameter has the bit 0 clear for not equal stripe sizes.Signed-off-by: Oliver Brown
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For i.MX6 ARD board, the board not support read EDID from TV,
so HDMI driver will create a default support mode list when system
bootup.
Because yocto xserver can not get video mode information from
framebuffer now, and xserver will set default video mode XGA
to framebuffer, but XGA mode is not support by hdmi.Remove XGA and SXGA from default support list.
HDMI driver will find a nearest match video mode in support list.
It is VGA mode. HDMI support VGA mode well.
Issue is fixed.Signed-off-by: Sandor Yu
19 Feb, 2014
14 commits
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This patch extracts the register init code for ESAI along with the default slot
number which is more common to I2S and LEFT_J mode.Acked-by: Wang Shengjiu
Signed-off-by: Nicolin Chen
(cherry picked from commit ad9c7ab4ff75488c0cc44bcc5d87af2d5d1139cf) -
This patch sets ESAI as LEFT_J format master so as to let ESAI provide bit
clock and frame clock for stability.Acked-by: Wang Shengjiu
Signed-off-by: Nicolin Chen
(cherry picked from commit 38df16f71c95e2aa8e0b4c1ddd2ed7ec2c4fef4b) -
This patch mainly adds the clock route from external 24.576MHz OSC to internal
ESAI clock via analog clock2 PADs on the SoC and pll4 so that ESAI can get an
entirely synchronous clock source against CS42888.[ 1, We found if using pll4 to generate a 24.576MHz from inernal 24.0MHz OSC,
we would get noise during the audio playback via ESAI->CS42888 even though
this generated clock's rate is equal to the external one statistically. It
might be resulted from the tiny difference between two clock source, which
might be crucial to the sensitive CODEC we use -- CS42888. So we here apply
the old 3.0.35 way to feed ESAI the same clock source as CS42888.2, Ideally, we should use bypass mode for pll4 since we only need to get
the raw rate (24.576MHz) while currently bypass mode in clk-pllv3.c isn't
entirely supported: The clock rate would be fixed to 24.0MHz if setting to
bypass, which would cause child clock get an incorrect rate and the driver
who uses the child clock fail to derive a needed clock rate, and it might
be dangerous to involve the clk-pllv3.c driver to this fix. Thus we here
apply 3.0.35 way provisionally. ]Expected result:
anaclk2 0 1 24576000
lvds2_in 0 1 24576000
pll4_sel 0 1 24576000
pll4_audio 0 1 786432000
pll4_post_div 0 1 786432000
pll4_audio_div 0 1 786432000
esai_sel 0 1 786432000
esai_pred 0 1 98304000
esai_podf 0 1 24576000
esai 0 1 24576000Acked-by: Wang Shengjiu
Signed-off-by: Nicolin Chen
(cherry picked from commit 49584be724d4d9c7a753d2b981b3932d8d871eb4) -
We actually have lvds2 (analog clock2), an I/O clock like lvds1, in the SoC.
And this lvds2, along with lvds1, can be used to provide external clock source
to the internal pll, such as pll4_audio and pll5_video.So This patch mainly adds the lvds2 to the clock tree and fix its relationship
with pll4 accordingly.[ To reduce the risk from code changing. This patch only takes care of pll4
related part. We might later need to add the relationship with pll5 too. ]Acked-by: Wang Shengjiu
Signed-off-by: Nicolin Chen
(cherry picked from commit 5b74b6b26e4b44d265090fc6ad15b15ccb7b5cff) -
All of these functions might be called before we enable the core clock in the
startup() by set_bias_level() or late_probe() in machine driver for example.
To make it safe, we here add pair of clock en/disabling to each function.Acked-by: Wang Shengjiu
Signed-off-by: Nicolin Chen
(cherry picked from commit e6df36df2bc8062f3d1c0a19d18acc843a77619d) -
This patch removes the function imx6q_lvds_cabc_init() from the
machine layer since we have a dedicated Hannstar CABC driver to
control the CABC feature.Signed-off-by: Liu Ying
(cherry picked from commit b0d2154a9c63b2beba774e46b90ec3d55609c672) -
This patch removes the device tree node lvds_cabc_ctrl, since
it is replaced by hannstar_cabc_lvds0 and hannstar_cabc_lvds1.Signed-off-by: Liu Ying
(cherry picked from commit 6a3d2c5e858afeef695bcd9fe2ecc0933d3d29da) -
This patch adds a device tree node for the Hannstar CABC function.
We currently disable the CABC feature since it makes a panel's
backlight unstable when display content varies considerably from
time to time.Signed-off-by: Liu Ying
(cherry picked from commit 0c98df5d1b04ea043e5279628aebf406c250f5e3) -
This patch adds a device tree node for the Hannstar CABC function.
The LVDS0 and LVDS1 interfaces of the i.MX6dql Sabreauto platform
shares a control pin for the CABC function, but LVDS1's control
wire is invalid for the unpopulated resistor R265 on the main board.
We currently disable the CABC feature since it makes a panel's
backlight unstable when display content varies considerably from
time to time.Signed-off-by: Liu Ying
(cherry picked from commit 6af4f4ac7c361a60fe05400497f644db3adcfc94) -
This patch enables the Hannstar CABC driver in imx_v7_defconfig.
Signed-off-by: Liu Ying
(cherry picked from commit 9eeaeb6a259af6864a6db563100a300ba67ed83e) -
This patch documents the Hannstar CABC driver's device tree bindings.
Signed-off-by: Liu Ying
(cherry picked from commit 0a6b9cf8548ffe03b8df494d08bece54ef3e528e) -
This patch adds Hannstar CABC driver support. The CABC
function turns the backlight density of a display panel
automatically according to the content shown on the panel.
It is controlled(enabled/disabled) by a GPIO.Signed-off-by: Liu Ying
(cherry picked from commit 2dddbc55bd8ae9461067e1a9d047b2994510e6d8) -
The bottom 16KB of the IRAM is reserved for the IRAM page table.
Reduce the available IRAM size for the other drivers by 16KB.Signed-off-by: Ranjani Vaidyanathan
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Whenever DDR is explicitly put into self-refresh, we need to ensure
that no access are made to the DDR. All the bus masters excpet ARM
are shutdown gracefully.
The ARM core can continue to access the DDR due to:
1. Speculative accesses
This can be prevented by flushing the Branch Target Address Cache
2. Aggressive Prefetching
This can be minimized by adding nops.
Apart from this the TLB architecture in ARM does not guarantee that
an entry remains in the TLB unless its explicitly locked. Even if
free slots are available an entry maybe evicted. So flushing the TLB
does not guarantee a page table walk will not happen.The solution is to put a minimized page table in IRAM that can be used when
DDR is in self-refresh. The IRAM page tables should have entries for IRAM,
AIPS1 and AIPS2 as these entries will be needed by the code that puts DDR
into self-refresh. It should not contain any entries that point to the DDR.This patch set accomplishes the following:
1. Set the IRAM to be mapped as 1M sections in the high mem region.
This makes it possible to create entries for the IRAM code in the IRAM page table.
We need to ensure that both the DDR and IRAM page table have mapping for the IRAM code.
2. Ensure the IRAM, AIPS1, AIPS2 have entries in the IRAM page table.
3. Save TTBR1
4. Set TTBR1 to point to the page tables stored in IRAM. Switch to using
TTBR1 before DDR is put into self-refresh. Ensure the following settings:
a. TTBCR.N = 1
This means the 0-2G virtual address space is translated using TTBR0
and 2G-4G is translated using TTBR1.
b. Set TTBCR.PD0 = 1
With this setting page table walks using TTBR0 are disabled.
4. After the DDR has exited self-refresh, reset TTBCR to 0 (TTBR0 will
be used for translations now).
5. Restore TTBR1Even though TTBR1 is only used to decode the top 2G of virtual address
space, ARM requires that we allocate the entire 16KB for the page table.
To minimize IRAM/OCRAM required, we put the code in the bottom 8K and
page table entries in the top 8K.
This requires the low power code be optimized to occupy as little space
as possible.Signed-off-by: Ranjani Vaidyanathan