09 Jun, 2017
40 commits
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Default compile the usdhc driver into kernel
Signed-off-by: Haibo Chen
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Fix the same issue as commit bf23e0c5ea31 on imx6qp-saresd-hdcp board
Signed-off-by: Robin Gong
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Fix below pfuze probe issue by setting correct range of SW3B:
pfuze100-regulator 0-0008: pfuze200 found.
SW3B: Bringing 3300000uV into 1975000-1975000uV
SW3B: failed to apply 1975000-1975000uV constraint(-22)
pfuze100-regulator 0-0008: register regulatorSW3B failed
pfuze100-regulator: probe of 0-0008 failed with error -22
2020000.serial: ttymxc0 at MMIO 0x2020000 (irq = 19, base_baud = 5000000) is a IMXSigned-off-by: Anson Huang
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Add USB OTG1 port ID pin for imx6ul-14x14-evk.dts
Acked-by: Peter Chen
Signed-off-by: Li Jun -
Add USB OTG1 port ID pin for imx6ull-14x14-evk.dts
Acked-by: Peter Chen
Signed-off-by: Li Jun -
Correct CD/WP pin in dts. Otherwise the card detection and write
protection function does not work.Signed-off-by: Dong Aisheng
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According to RM, Bit[11-8] is MUX_MODE which is configured by
the PIN_FUNC_ID automatically, specify it in config part is wrong
and violates the binding doc. So remove them all.It can also avoid the future confusing when customer wants to
configure a pad by following the exist code.Signed-off-by: Dong Aisheng
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Add i.MX7ULP binding doc. Note i.MX7ULP PIN_FUNC_ID consists of 4
integers as it shares one mux and config register as follows:Also fix the copyright.
Signed-off-by: Dong Aisheng
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'vin-supply' property used in ldo-bypass mode while 'vin-supply' deleted
in ldo-enable mode on v4.9 rather than dirctly switch 'supply' to internal
regulator and external pmic regulator on v4.1. Correct it for all *-ldo.dts,
otherwise, still work in ldo-bypass mode.Signed-off-by: Robin Gong
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I2C2 have to be disabled on hdcp board since those I2C2 bus pins
used for others, that said there is no all pmic regulators. In this
case, ldo-enable mode should be used and reg_arm/reg_soc/reg_pu should
be swithed to internal ldo instead. Otherwise, no reg_pu regulator
probed successfully by gpu driver, and cause gpu probe failed. Also,
cause cpufreq probe failed too.Signed-off-by: Robin Gong
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For wm8962 we use imx-wm8962 machine driver which expects DAI CPU node
name to be "cpu-dai".Signed-off-by: Daniel Baluta
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Commit 65e6b5f1b4a7 ("ASoC: wm8960: Fix playback in CPU DAI master
mode") broke wm8960 codec master mode by choosing "bad" SYSCLK values.This patch partially reverts commit mentioned above by restoring the
SYSCLK values. It turns out that using params_physical_width instead of
params_width in the previous patch it is enough to fix CPU DAI mode.Signed-off-by: Daniel Baluta
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Commit 556fa2d7d7e9 ("ENGR00318895-9: mtd: spi-nor: add more read
transfer flags for n25q256a") was incompletely cherry-picked, leaving
out the removal of the SECT_4K flag:"From the datasheet, the chip support the 64K sector erase operation.
So remove the SECT_4K for the chip which makes the flash_erase
faster."However, the above statement is not entirely correct. Using SECT_4K
can result in faster erase operations, if the block to erase is
smaller. The documentation in spi-nor.c also states:"All newly added entries should describe *hardware* and should use
SECT_4K (or SECT_4K_PMC) if hardware supports erasing 4 KiB
sectors. For usage scenarios excluding small sectors there is config
option that can be disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS. For
historical (and compatibility) reasons (before we got above config)
some old entries may be missing 4K flag."Unfortunately, using SECT_4K means that ubifs will fail, because it
needs a minimum LBE of 15K.Based on the above comments, it looks like the best way to handle the
ubifs issue is to disable CONFIG_MTD_SPI_NOR_USE_4K_SECTORS instead of
removing SECT_4K for the particular n25q256a chip. This approach also
has the advantage that will make ubifs work with any chip that has the
SECT_4K flag.Signed-off-by: Octavian Purdila
Reviewed-by: Han Xu -
Without this information probing of imx-rpmsg fails as it is not able
to setup the vring due to missing allocated physical memory.Signed-off-by: Octavian Purdila
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To keep backward compatibility of the default device tree settings,
we should set HDMI's display interface to be DI0 of IPU0.
This makes HDMI and MIPI DSI be able to work simultaneously on the
i.MX6q/qp sabresd platform. Also, LVDS1 and HDMI on the i.MX6sdl
sabresd platform.So, let's revert "MLK-14678: dts: Fix lcd display id"
(commit 85073fc130e83a1cfba58f0f06d9d8cbbd8c88f4).Signed-off-by: Liu Ying
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Original frequency 786.432MHz can't be divide to frequency 2.304MHz
which is needed by 48kHz/24bit/2channel, So update the pll frequency
for 24bit case.Signed-off-by: Shengjiu Wang
Reviewed-by: Daniel Baluta -
- Add BT modem device reset node for SCM i.MX6 devices
- Add Wifi OOB support for QWKS rev3 and EVBSigned-off-by: Juan Gutierrez
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- replace legacy wakeup property with 'wakeup-source'
- add "jedec,spi-nor" flash compatible binding
- fix lcd display id
- fixig typo for gpios
- use external wdog_b reset instead of issuing a sw reset
- add off-on-delay for usdhc vmmc-supply regulator on mx6sxscm
- add missing sai1 and wdog1 configs for mx6sxscm
- fix vgen6 regulator maximum microvolt for mx6dqscm
- disable CAAM since cannot coexist with LCDIF for mx6sxscm
- add the reg into the rpmsg node for mx6sxscmSigned-off-by: Juan Gutierrez
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With the current rates for MCLK is not possible to derive bitclk
for all files in S20_3LE format and also for files with S24_LE sampled
at 48000Hz.In order to fix this, we need to find a better MCLK value. We did this
in two steps:
1) Use params_physical_width to get rid of S20_3LE burden.
2) Brute force into all available rates which can pass fsl_sai_set_bclk
algorithm.Thus we found 36864000 to be the smallest acceptable rate for MCLK.
Reviewed-by: Mihai Serban
Suggested-by: Shengjiu Wang
Signed-off-by: Daniel Baluta -
The reg_lcd_3v3 regulator is, theoretically, used by the display
controller eLCDIF as lcd supply.When enabling the HDMI trasnmitter Sil902x, a gpio pin needed by the
regulator is taken by the HDMI TX as reset pin, so the regulator probe
fails and is never used.The imx6sx-sdb-lcdif1.dts file is used for HDMI functionality, thus
enabling the HDMI transmitter invalidates any possible use of the
reg_lcd_3v3 regulator.This patch removes the regulator enablement from the HDMI-specific dts.
Signed-off-by: Cristina Ciocan
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The default display engine used by lcd in imx6qdl-sabresd.dtsi is IPU:0
DI:0, the same used for hdmi. This is a conflict, and every time the
kernel boots, this error will be printed:
mxc_sdc_fb fb@2: ipu0-di0 already in use
mxc_sdc_fb: probe of fb@2 failed with error -16
And, of course, lcd cannot be used in parallel with hdmi.
In order to fix this, move hdmi to IPU:0 DI:1. I left lcd to IPU:0 DI:0
because it works only with that IPU core.Signed-off-by: Robert Chiras
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The mxc display driver framework doesn't support deferral probe.
The following initialization process may cause the mipi dsi driver
deferral probe, however.
pinctrl-imx6 - arch_initcall
gpio-mxc - subsys_initcall
gpio-reset - arch_initcallThis patch customizes gpio reset function so that we can remove
the code to use the reset logic provided by the gpio-reset driver.
Also, the gpio-reset driver is not in the upstreaming kernel,
so it would be good not to use it if possible.Signed-off-by: Liu Ying
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The automated CI system will check if the configuration files are
generated by the 'make savedefconfig' command from now on.
We have to create a correct starting point to pass the checks.Signed-off-by: Mihai Serban
Reviewed-by: Octavian Purdila -
Update ERA detection code to check 3 sources CCBVID, CAAMVID
and the device tree.
Fix bit handling of CAAMVID data to obtain correct results.
Remove default device tree values.
Update errata handling to target known affected platforms.Signed-off-by: Radu Solea
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Add the new property 'dsi-traffic-mode' which is used to
set one of the three video data transmit modes:
. Non-burst mode with sync pulse width
. Non-burst mode with sync event
. Burst modeSigned-off-by: Fancy Fang
(cherry picked from commit 19eb160cfa365af6a377798cf44dc800f21ef51d) -
Correct right RUN mode after A7 resume back instead of the VLLS mode
Signed-off-by: Robin Gong
(cherry picked from commit f6b3dda9babd17fcbab5fc2b05c3f64660ea6250) -
Update the setpoint voltage on i.MX7ULP.
Signed-off-by: Bai Ping
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ISOACK must be done only after all IOMUX/GPIO settings done,
otherwise, some PADs can NOT keep state during VLLS
enter/exit and cause some pins toggling, and lead to
external devices in abnormal state, like reset etc..This patch does all iomux/gpio settings restore in VLLS exit
flow, since DDR PADs need to be functioning before jump
to DDR, so isoack can only be done in ASM code, to save
OCRAM space, all pins in port C - F will be restored, even
some pins are reserved, but read/write these reserved pins
settings are OK on i.MX7ULP.Signed-off-by: Anson Huang
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From testing the performance is better when the voltage
for lpddr2 is set to 1.25V instead of 1.2V.Signed-off-by: Juan Gutierrez
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Since regulator reg_vsd_3v3b for SD1, and has pin confict with lpuart,
then move the regulator to SD1 specific dts file.Signed-off-by: Fugang Duan
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On i.MX7D low power idle, consider below scenario which has
race condition that low power idle is entered unexpectedly
for first CPU:CPU#1 enters low power idle:
1. set last_cpu to invalid -1;
2. set cpu1_wfi in low level ASM code;
3. enter WFI;
CPU#0 enters low power idle:
4. set last_cpu to CPU#0;
5. Set hardware(DDR, CCM, ANATOP) to low power idle mode;
6. enter WFI;If during 4~6 window, CPU#1 go out of WFI and then go into low
power idle again, the condition check of master_lpi will be true
and CPU#1 will go through 4~6 steps in low level ASM code,
which is unexpected. As cpu_cluster_pm_enter/exit can only be called
once for last cpu in same cluster.To avoid this race condition, add last_cpu check as well as master_lpi
check, that means if last_cpu is a valid value, the other CPU entering
low power idle will be treated as first CPU. And also move the setting
of last_cpu to invalid value to last CPU low power idle exit path.Signed-off-by: Anson Huang
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On A2 board, NVCC_DRAM_SW power control is changed from PTC1
to PTB6, and PTB6 will be controlled by M4, so A7 does NOT
need to control this pin during VLLS, M4 will do it.Signed-off-by: Anson Huang
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Add inline for unused function to avoid build warning.
For example, when i.MX7D is unselected, below warning
will show during compile:arch/arm/mach-imx/common.h:163:13: warning:
'imx_gpcv2_add_m4_wake_up_irq' defined but not used
[-Wunused-function]Signed-off-by: Anson Huang
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For the slot support SD3.0 card, during system suspend, if plug out
the sd card, and insert another SD3.0 card, after system resume back,
SD3.0 card can't be recognised as SD3.0 card, just SD2.0 card.This is bause the time delay between vmmc regulator off and on is
too small, this patch add the oo-on-delay in vmmc-supply regulator,
to assign proper delay value.Signed-off-by: Haibo Chen
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Move the default arm/soc-supply property define in imx6ull
dtsi file.Signed-off-by: Bai Ping
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The default touch panel parameters in the dts file is used for the maximum supported display resolution.
It needs to calibrate the touch panel to match other resolution display screen.
The display screen for mx7ulp-evk is not matched the default parameters.change the dts file, so it need not to calibrate the touch panel for mx7ulp-evk board.
Change-Id: I24b1ceeef7f584b6ddf057794271dfa3a5875c0b
Signed-off-by: Zhang Bo
Signed-off-by: Gao Pan
(cherry-pick from 670d180d907c9bada3972ac9aded51a1becaf646) -
Add rpmsg-keys driver on i.mx7ulp-evk board since vol+/vol- keys
are connected on m4 side and have to get the status of keys by
rpmsg.Signed-off-by: Robin Gong
[Irina: updated for 4.9 APIs]
Signed-off-by: Irina Tirdea -
There is noise when use ssi master mode. the reason is the ssi rate
is not accurate for ssi master mode, show below.pll3_pfd2_508m 0 0 508235294 0 0
ssi3_sel 0 0 508235294 0 0
ssi3_pred 0 0 127058824 0 0
ssi3_podf 0 0 63529412 0 0
ssi3 0 0 63529412 0 0
ssi2_sel 0 0 508235294 0 0
ssi2_pred 0 0 127058824 0 0
ssi2_podf 0 0 63529412 0 0
ssi2 0 0 63529412 0 0so we need to switch ssi's parent to pll4 (which is dedicate audio pll),
and set a proper rate for pll4, we select 786432000Hz, which can
generate 32kHz,48kHz,96KHz.Signed-off-by: Shengjiu Wang
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enable sim for imx6ul
Signed-off-by: Gao Pan
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Sensors are connected to M4 and not to A-Core.
Sensors will not be exposed to A-Core via standard
i2c interface but via an i2c proxy layer over rpmsg.Remove the dts entry to avoid the probe error messages and
add a separate dts file for the case where someone wishes to
rework the board themselves and connect sensors for testing purposes.Signed-off-by: Adriana Reus