19 Nov, 2020
1 commit
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Add mode_valid() implementation for CRTC to filter out any
mode which cannot be supported by LCDIFv3. Only check the
CEA and DMT modes for pixel clock round rate is same with
the value from mode.Signed-off-by: Fancy Fang
Reviewed-by: Liu Ying
(cherry picked from commit f252a44da9f90951614c0bf513df6bd4d145e76e)
09 Jul, 2020
3 commits
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This patch adds user-configurable CRC region support.
The users may choose a region of interest(ROI) as the CRC source
(i.e., the CRC evaluation window) via the debugfs control node.
The ROI cannot exceed the display region as indicated by
drm_crtc_state->adjusted_mode. The users may write a string in
the fashion of "roi:x1,y1,x2,y2" to the node to specify the ROI
within the display region. The inclusive position at (x1, y1)
indicates the upper left of the region, while the exclusive
position at (x2, y2) indicates the lower right of the region.Signed-off-by: Liu Ying
Reviewed-by: Robby Cai -
This patch adds helper disengcfg_sig_select() support so that
users may select different taps(FrameGen, GammaCor, Matrix or
Dither) to do signature computation. Also, select FrameGen as
the default tap in _dpu_dec_init() and call it in dpu_dec_init().Signed-off-by: Liu Ying
Reviewed-by: Robby Cai -
This patch adds signature unit support in the dpu common driver.
Signed-off-by: Liu Ying
Reviewed-by: Robby Cai
15 May, 2020
1 commit
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After the atomic plane update, the shadow load should be
enabled to make sure its update can take effect on next
frame in any cases. And this enable is better to be done
in CRTC's atomic_flush() which is called after plane's
atomic_update() is called.Besides, the shadow load enable in controller enable is
unnecessary, so remove it.Signed-off-by: Fancy Fang
Reviewed-by: Liu Ying
26 Feb, 2020
2 commits
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This patch adds helper dprc_disable_repeat_en() so that callers
may disable DPRC repeat_en.Reviewed-by: Sandor Yu
Signed-off-by: Liu Ying
(cherry picked from commit 37b68e353a2dc8e3370fb27a4aebf42f5da63047) -
No one is using pin-off operations, so let's remove them.
Reviewed-by: Sandor Yu
Signed-off-by: Liu Ying
(cherry picked from commit 7243d962bb29a35ba4ee1328bdb5d011cf1471cd)
15 Jan, 2020
1 commit
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The LCDIFv3 core driver is responsible to provide
controller registers configuration and create the
platform devices for the child port nodes. And the
platform devices later will attach to the related
DRM/KMS drivers via name match. And the LCDIFv3 is
completely different from the LCDIF controller
which is used on imx8mm and imx8mn platforms.Signed-off-by: Fancy Fang
02 Dec, 2019
5 commits
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* mxc/next: (119 commits)
mxc: hdmi-cec: Add imx6 hdmi cec driver
driver: mfd: hdmi: Add hdmi core driver
MLK-22399 mxc IPUv3: cpmem: Get 0 u/v_offset in __ipu_ch_offset_calc() for some pfmts
mxc: IPU3: Fix not including uapi/linux/sched/types.h
media: platform: mxc: output: Forward IPUv3 V4L2 output driver from imx_4.19.y
... -
* origin/display/prefetch:
MLK-21378-2 gpu: imx: Add imx8_dprc support
MLK-21378-1 gpu: imx: Add imx8_prg support
gpu: Move ipu-v3 to imx folder
drm/imx: Revert a patch which merges imx-drm-core and ipuv3-crtc in one module -
* origin/display/pc:
gpu: imx: Add imx8 pixel combiner support
gpu: Move ipu-v3 to imx folder
drm/imx: Revert a patch which merges imx-drm-core and ipuv3-crtc in one module -
* origin/display/lcdif: (32 commits)
gpu: imx: lcdif: add imx8mn compatible support
drm/imx: Replace reset flow for LCDIF
gpu: imx: lcdif: fix build warnings if CONFIG_PM_SLEEP off
drm/imx: lcdif: change DISPMIX reset for IMX8MN
MLK-21876-10 gpu: drm: lcdif: fix headfile reference issue
... -
* origin/display/fbdev: (26 commits)
MLK-22768 video: fbdev: mxc_ipuv3_fb: Handle enabled fg properly when set-par happens on bg
video: fbdev: mxsfb: Fix writecombine/wc build error
MLK-22084: fbdev: hdmi: Fix HDCP function failed work with Sony TV
fbdev: dcic: Enable imx6 dcic driver
video: fbdev: mxc: hdmi: add hdmi framebuffer driver
...
25 Nov, 2019
27 commits
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Add the framebuffer driver support for the Northwest Logic
MIPI DSI controller.Signed-off-by: Fancy Fang
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According to LCDIF specification, the input pixel data
width and the output pixel data width can be different,
and this conversion is done by LCDIF automatically. So
config the output data width according to the requested
bus format from the encoder, instead to be same with the
input pixel data width.Signed-off-by: Fancy Fang
(cherry picked from commit bfd27f6d71d86a7f2fc8314f082565db3682b925) -
According to the LCDIF specification, the Legacy Mode does not
support cropping function in the horizontal direction, so add
Pigeon Mode which can support this kind of function. And when
enable this mode, the legacy horizontal timings configuration
should use stride value but not the active width, and related
pigeon configuration should use the active width but not the
stride value.Signed-off-by: Fancy Fang
(cherry picked from commit e6da9542693dd585972897f62748a101f5726a74) -
Add an function to get the LCDIF controller supported bus
formats according to the pixel format bpp. And change the
bus format sanity check in the plane's atomic check to see
if the bus format required by the peripheral attached to
LCDIF can be supported by LCDIF.Signed-off-by: Fancy Fang
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The LCDIF core driver is responsible to provide controller
registers configuration and create the platform devices for
the child port nodes. And the platform devices later will
attach to the corresponding DRM/KMS drivers via name match.Signed-off-by: Fancy Fang
[ Aisheng: Kconfig & Makefile update for a clean base ]
Signed-off-by: Dong Aisheng -
This patch adds i.MX8 pixel combiner driver support.
Signed-off-by: Liu Ying
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Fast-forward imx8_dprc driver from imx_4.14.y.
Signed-off-by: Liu Ying
[ Liu Ying: scfw call updates and other small tweaks for upgrade] -
Fast-forward imx8_prg driver from imx_4.14.y.
Signed-off-by: Liu Ying
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As DPU fetchunits support ITU601(limited range)/ITU601_FR(full range)
and ITU709(limited range) YUV to RGB color space conversions, we may
add color encoding and color range properties support for planes.
Considering software backward compatibility, the default color encoding
is set to ITU601 with full color range.Signed-off-by: Liu Ying
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This patch adds mulitple pixel blend modes for DPU plane.
The modes are "None", "Pre-multiplied" and "Coverage".Signed-off-by: Liu Ying
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Without the new blend modes("None", "Pre-multiplied" and "Coverage")
introduced in the below commit, the old userspace assumes alpha in
pixel is per-premultiplied by default. So, let's support the default
blend mode properly.commit a5ec8332d428 ("drm: Add per-plane pixel blend mode property")
Signed-off-by: Liu Ying
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This patch adds extdst_pixengcfg_syncmode_master() helper support
so that the callers may control if a extdst is master or slave
when it works in sync mode. The bit16 of extdst's PIXENGCFG_STATIC
register controls this and it's a part of sync mode fixup logic.Signed-off-by: Liu Ying
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Bit7 of framegen's SECSTATCONFIG register is used to control
the sync mode fixup logic implemented in framegen. This patch
adds framegen_syncmode_fixup() helper so that the callers
may enable/disable the fixup logic for a framegen.Signed-off-by: Liu Ying
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Store9 unit can be shared bewteen display engine(for sync mode fixup)
and blit engine. It's proper to get the store resource in the DPU
common driver and then provide it to client platform device via
platform data.Signed-off-by: Liu Ying
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Bit16 of store9's PIXENGCFG_STATIC register is used to control
the sync mode fixup logic implemented in store9. So, let's
add store9 support in the DPU core driver and export a function
for users to enable/disable the fixup logic.Signed-off-by: Liu Ying
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This patch adds pixel combiner support in the DPU core driver.
Users may get and enable/disable/control a pixel combiner instant
via tcon functions and may tell if it is needed in a specific usecase
via the dpu_get_syncmode_min_prate() and dpu_get_singlemode_max_width()
helpers.Signed-off-by: Liu Ying
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This patch adds side-by-side support for tcon so that
two tcons can participate in the dual display streams
to work with pixel combiner to drive a high pixel rate
display.Signed-off-by: Liu Ying
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This patch adds side-by-side support for framegen so that
two framegens can work in sync mode to participate in the
dual display streams to drive a high pixel rate display
via a pixel combiner.Signed-off-by: Liu Ying
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This patch adds tcon_is_master/slave() helpers support so that
callers may know if a tcon is a master or slave tcon.Signed-off-by: Liu Ying
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This patch adds extdst_is_master() helper support so that
callers may know if a extdst is a master extdst or not.Signed-off-by: Liu Ying
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This patch adds framegen_is_master/slave() helpers support so that
callers may know if a framegen is a master or slave framegen.Signed-off-by: Liu Ying
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This patch adds helper dpu_get_master_stream_id() support
so that callers may know the master stream when FrameGen
works in sync mode.Signed-off-by: Liu Ying
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This patch adds a new di_grp_id entry in display client pdev's data
so that the relevant display platform driver may know the display
group ID of the display device.Signed-off-by: Liu Ying
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This patch adds dpu_aux_{unit}_peek() helpers so that callers
may peek at auxiliary display submodules.Signed-off-by: Liu Ying
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The CRTC background should be full screen instead of partial
screen, because the DRM core is likely to add configurable
background color support in the future. We may cover the full
screen with ConstFrame0/1, upon which builds planes. With this,
it is easier to compute each plane's layer offset vs CRTC start
point and all ConstFrame units can be controlled by CRTC.Signed-off-by: Liu Ying
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This patch adds two helpers to get and clear FrameGen secondary channel
status respectively. Via the two helpers, users may know if there is
empty FIFO read request on this channel or not after getting the status.
And, if yes, users may choose to clear the status. According to the IP
spec, the empty FIFO read request indicates that data stream from a Fetch
unit(e.g., AXI bandwidth not sufficient) fell down. Assuming the display
driver sets things up properly, the falling down is very likely caused by
the insufficient AXI bandwidth, that is, display underrun.Signed-off-by: Liu Ying
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To workaround the errata TKT320950, DPR/PRG need to evade the first dumb frame
which is generated by DPU. The way we achieve that is to bypass TCON(but set
the TCON sync signals and KA_CHUCK strobe signal up) before enabling the DPU
display controller, and then 1) enable the display controller, 2) wait for the
frame index starting to move and 3) finally switch TCON to operation mode.
Steps 1) to 3) should be done within a frame, so we disable local irq and
preemption to make sure we don't relinquish CPU during the procedure.Signed-off-by: Liu Ying