09 May, 2012

1 commit

  • Tegra AHB Bus conforms to the AMBA Specification (Rev 2.0) Advanced
    High-performance Bus (AHB) architecture.

    The AHB Arbiter controls AHB bus master arbitration. This effectively
    forms a second level of arbitration for access to the memory
    controller through the AHB Slave Memory device. The AHB pre-fetch
    logic can be configured to enhance performance for devices doing
    sequential access. Each AHB master is assigned to either the high or
    low priority bin. Both Tegra20/30 have this AHB bus.

    Some of configuration params could be passed from DT too if needed.

    Signed-off-by: Hiroshi DOYU
    Acked-by: Arnd Bergmann
    Cc: Felipe Balbi
    Signed-off-by: Stephen Warren

    Hiroshi DOYU