07 Apr, 2017
2 commits
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Remove unused code reserved for upcoming CPUs.
Reported-by: Dan Carpenter
Signed-off-by: Sergey Temerkhanov
Cc: David Daney
Cc: Jan.Glauber@cavium.com
Cc: linux-edac
Link: http://lkml.kernel.org/r/20170406113834.17153-1-s.temerkhanov@gmail.com
Signed-off-by: Borislav Petkov -
Shift the node number by 3 bits instead of 8 allowing proper functioning
with default EDAC_MAX_MCS.Signed-off-by: Sergey Temerkhanov
Cc: David Daney
Cc: Jan.Glauber@cavium.com
Cc: linux-edac
Link: http://lkml.kernel.org/r/20170406113755.17082-1-s.temerkhanov@gmail.com
Signed-off-by: Borislav Petkov
05 Apr, 2017
1 commit
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Fix a typo that disabled the MCI interrupts using the wrong bitmask.
Signed-off-by: Jan Glauber
Cc: David Daney
Cc: Ralf Baechle
Cc: Sergey Temerkhanov
Cc: linux-edac
Link: http://lkml.kernel.org/r/20170405102739.6301-1-jglauber@cavium.com
Signed-off-by: Borislav Petkov
27 Mar, 2017
1 commit
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Add support for Cavium ThunderX EDAC capable on-chip peripherals, namely
the DRAM controller (LMC), cache coherent processor interconnect (CCPI)
and level 2 cache blocks (L2C-TAD, L2C-MCI, L2C-CBC)Signed-off-by: Sergey Temerkhanov
Cc: David.Daney@cavium.com
Cc: Jan.Glauber@cavium.com
Cc: linux-edac
Link: http://lkml.kernel.org/r/20170324222837.60583-1-s.temerkhanov@gmail.com
Signed-off-by: Borislav Petkov