18 Jan, 2021
2 commits
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The low memory space is limited by vmalloc size as they share kernel space.
The vmalloc upper limit space is 0xff000000.
And register map space must reside in vmalloc space.
If register map address is 0xf4000000, vmalloc size must be large than
0xff000000 - 0xf4000000 = 176M.
Change Special register map address to high space, so vmalloc size can be small.Change-Id: Ia51f8b2a10c25e2f0cb1d3842d565000e7a6a23c
Signed-off-by: Xiaowen Liu -
The upper limit address of vmalloc is 0xff800000. AIPS virtual map address
should be in vmalloc address space. In order to use smaller vmalloc
size, the AIPS map address should be high enough. Set the AIPS map
address to 0xf8000000, so the minimum vmalloc size can be 120M.Change-Id: I5abdf123efbeaa8e2791c5572005429f8b77210e
Signed-off-by: Zhang Bo
13 Jan, 2021
1 commit
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For imx7ulp PM_SUSPEND_MEM mode, all port related register will lost.
This patch add the save/restore operation. This will benefit gpio-irq.
Without this patch, gpio irq can't work after system PM.
This patch depend on the dts file, the sequence of gpio definition must
be gpio_ptc gpio_ptd gpio_pte gpio_ptf.Signed-off-by: Haibo Chen
Acked-by: Jacky Bai
14 Dec, 2020
37 commits
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Some DT node path are changed, correct them to support i.MX7D 12x12 LPDDR3
validation board.Signed-off-by: Anson Huang
Reviewed-by: Jacky Bai -
The commit eb1f00237aca ("lockdep,trace: Expose tracepoints"), started to
expose us for tracepoints. For i.MX7D cpuidle, this leads to an RCU splat
according to below.[8.613615] [] (_raw_spin_lock_irqsave) from [] (imx_gpcv2_set_lpm_mode+0x10/0xd8)
[8.622966] [] (imx_gpcv2_set_lpm_mode) from [] (imx7d_enter_low_power_idle+0x184/0x370)
[8.632836] [] (imx7d_enter_low_power_idle) from [] (cpuidle_enter_state+0xc8/0x644)To fix the problem, add CPUIDLE_FLAG_RCU_IDLE to idlestate->flags, which
enables us to call rcu_idle_enter/exit() at the proper point.Signed-off-by: Anson Huang
Reviewed-by: Jacky Bai -
commit d01f449c008a ("of_net: add NVMEM support to of_get_mac_address")
introduces more return value types, so it has to use IS_ERR to check
the return value.Reviewed-by: Richard Zhu
Signed-off-by: Fugang Duan -
HAVE_IMX_RPMSG depends on IMX_MBOX which should also be selected.
otherwise we meet below build errors:arm-poky-linux-gnueabi-ld: arch/arm/mach-imx/pm-rpmsg.o: in function `pm_heartbeat_probe':
pm-rpmsg.c:(.text+0x14): undefined reference to `__register_rpmsg_driver'
arm-poky-linux-gnueabi-ld: arch/arm/mach-imx/pm-rpmsg.o: in function `pm_send_message.constprop.0':
pm-rpmsg.c:(.text+0x94): undefined reference to `rpmsg_send'It was caused by RPMSG was not correctly selected by HAVE_IMX_RPMSG
due to unmet dependency.Signed-off-by: Dong Aisheng
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- When OPTEE OS is present and if it support the busfreq
for the running the i.MX, the busfreq is executed in
the OPTEE OS by calling a specific SMC function
- Only a WFE function is copied into the OCRAM to
synchronize all Cores in multi-core devices
- OPTEE OS add a DT property 'busfreq=1' in the 'firmware/optee'
node to indicate the busfreq supportSigned-off-by: Cedric Neveux
Signed-off-by: Arulpandiyan Vadivel -
When refresh i.MX7ULP wdog during resume, need to check if wdog is power
gate or NOT, as the command mode is different, if using incorrect refresh
command, it will trigger system reset immediately, so add CMD32 bit check
to make it work for both standby and mem mode suspend.Signed-off-by: Anson Huang
Reviewed-by: Jacky Bai
(cherry picked from commit 1645d2add2862bf09de5e18568f3351bc230ed21) -
i.MX7ULP's wdog1 is enabled by default when it is out of reset, the default timeout
value is 0x400 which is NOT safe enough to make sure NOT timeout before wdog driver
resume, so need to refresh wdog1 to buy more time for wdog driver resume which will
reconfigurate the wdog.Signed-off-by: Anson Huang
Reviewed-by: Jacky Bai
(cherry picked from commit c71292550b839884a36b4d81c757344f5018056e) -
On i.MX7ULP rev 2.2, the rev value is 3, so add support for this
revision, otherwise, it will use default revision of 1.0 which is
incorrect.Signed-off-by: Anson Huang
Reviewed-by: Jacky Bai
(cherry picked from commit 339538500b30ff2b264602bea594fc380a15e81c) -
Current RBC counter value of 0x8(~240us) is NOT enough to block interrupt
when entering low power mode, when interrupt arrives during the window of
GIC dist disabled and low power mode enter NOT finished, system will stuck
at WFI and never wake up, increasing RBC counter can avoid this situation,
since the latency introduced by RBC counter is quite trivial, so here just
use the MAX value of 0x3f(~2ms) to make it safe enough.Signed-off-by: Anson Huang
Reviewed-by: Jacky Bai
(cherry picked from commit 41fae930efd1b0c4e78c7e3419b81dacee39097e) -
When cpu runs in HSRUN mode, cpuidle is not allowed to run into
Stop mode. So add imx7ulp_get_mode to get thr cpu run mode,
and use WAIT mode instead, when cpu in HSRUN mode.Reviewed-by: Dong Aisheng
Signed-off-by: Peng Fan -
remove the unused node define & related code.
Signed-off-by: Jacky Bai
Reviewed-by: Anson Huang -
This file is newly created since
512a928affd5 ("ARM: imx: build v7_cpu_resume() unconditionally")
and missing is_cortex_a7 macro definition.Signed-off-by: Dong Aisheng
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67b06ba0 ("PM: QoS: Drop PM_QOS_CPU_DMA_LATENCY and rename related functions")
changed the pm_qos_*() APIs. Updated the IMX usage of them to the new
APIs.Signed-off-by: Li Yang
Signed-off-by: Dong Aisheng -
On i.MX6QP, the soc_id exported to the /sys/devices/soc0/soc_id
should be 'i.MX6QP'.Signed-off-by: Jacky Bai
Reviewed-by: Anson Huang
[ Aisheng: update changes to drivers/soc/imx/soc-imx.c ]
Signed-off-by: Dong Aisheng -
The latest DTB changes the AIPS bus node name, some of the DT
nodes are searched by DT path, need to update the path accordingly
to make suspend/resume work.Signed-off-by: Anson Huang
Reviewed-by: Jacky Bai -
Old API was hiddened from user.
../arch/arm/mach-imx/pm-imx6.c: In function ‘imx6_dt_find_lpsram’:
../arch/arm/mach-imx/pm-imx6.c:973:6: error: implicit declaration of function ‘of_flat_dt_match’ [-Werror=implicit-function-declaration]
973 | if (of_flat_dt_match(node, low_power_ocram_match)) {Signed-off-by: Dong Aisheng
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Old API was hiddened from user.
../arch/arm/mach-imx/busfreq-imx.c: In function ‘imx_dt_find_ddr_sram’:
../arch/arm/mach-imx/busfreq-imx.c:962:6: error: implicit declaration of function ‘of_flat_dt_match’; did you mean ‘of_flat_dt_match_machine’? [-Werror=implicit-function-declaration]
962 | if (of_flat_dt_match(node, ddr_freq_iram_match)) {Signed-off-by: Dong Aisheng
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Old API was hiddened from user.
../arch/arm/mach-imx/pm-imx7ulp.c: In function ‘imx7ulp_dt_find_lpsram’:
../arch/arm/mach-imx/pm-imx7ulp.c:559:6: error: implicit declaration of function ‘of_flat_dt_match’ [-Werror=implicit-function-declaration]
559 | if (of_flat_dt_match(node, low_power_ocram_match)) {
| ^~~~~~~~~~~~~~~~Signed-off-by: Dong Aisheng
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Old API was hiddened from user.
../arch/arm/mach-imx/pm-imx7.c: In function ‘imx7_dt_find_lpsram’:
../arch/arm/mach-imx/pm-imx7.c:891:6: error: implicit declaration of function ‘of_flat_dt_match’ [-Werror=implicit-function-declaration]
891 | if (of_flat_dt_match(node, low_power_ocram_match)) {
| ^~~~~~~~~~~~~~~~Signed-off-by: Dong Aisheng
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On i.MX6DL, AXI clock is from 540M PFD in normal mode, and from periph
clk in low bus mode, so need to make sure AXI clock parent switch
correctly in normal mode and low bus mode.Signed-off-by: Anson Huang
Reviewed-by: Jacky Bai -
Add cpu type check for i.MX6ULZ in MSL code to support low
power feature.Signed-off-by: Jacky Bai
Reviewed-by: Anson Huang -
enet_clk_ref is the same clock as ptp for i.MX6qdl platform,
but dtsi only define ptp clock that source from soc internal
anatop clock, and imx6q clock driver already register "enet_ref"
clock lookup for the ptp clock, so keep the con_id string as
"enet_ref" for clk_get_sys().This reverts commit a3990871b98587f53548e769c23fda5c2644063c.
Signed-off-by: Fugang Duan
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Remove unused code on i.MX7D suspend driver.
Signed-off-by: Anson Huang
Reviewed-by: Jacky Bai -
During system counter frequency change, the counter will stop, it
takes several mS even up to 20mS to finish the frequency change, if
system enters STOP mode before the frequency change done, system
counter will NOT run during STOP mode, then it will case system time
inaccurate and sometimes cause below RCU stall, so system can ONLY
enter STOP mode after the system counter frequency change done by
checking the ACK of frequency change.rtc_testapp_6 0 TINFO : Waiting 50 seconds for alarm.......
fec 30be0000.ethernet eth0: Link is Down
PM: suspend devices took 0.670 seconds
Disabling non-boot CPUs ...
Enabling non-boot CPUs ...
rcu: INFO: rcu_sched self-detected stall on CPU
rcu: 0-...!: (1 ticks this GP) idle=1f6/1/0x40000002 softirq=5240/5240 fqs=0
(t=4903 jiffies g=3737 q=4)
rcu: rcu_sched kthread starved for 4903 jiffies! g3737 f0x0 RCU_GP_WAIT_FQS(5) ->state=0x402 ->0
rcu: RCU grace-period kthread stack dump:
rcu_sched I 0 10 2 0x00000000
[] (__schedule) from [] (schedule+0x50/0xc4)
[] (schedule) from [] (schedule_timeout+0x1b8/0x37c)
[] (schedule_timeout) from [] (rcu_gp_kthread+0x8cc/0x1678)
[] (rcu_gp_kthread) from [] (kthread+0x114/0x14c)
[] (kthread) from [] (ret_from_fork+0x14/0x20)
Exception stack(0xd80fdfb0 to 0xd80fdff8)
dfa0: 00000000 00000000 00000000 00000000
dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
dfe0: 00000000 00000000 00000000 00000000 00000013 00000000
NMI backtrace for cpu 0
CPU: 0 PID: 834 Comm: rtc_testapp_6 Not tainted 5.4.0-rc7-03214-g56a9ca3 #105
Hardware name: Freescale i.MX7 Dual (Device Tree)
[] (unwind_backtrace) from [] (show_stack+0x10/0x14)
[] (show_stack) from [] (dump_stack+0xe4/0x118)
[] (dump_stack) from [] (nmi_cpu_backtrace+0xac/0xbc)
[] (nmi_cpu_backtrace) from [] (nmi_trigger_cpumask_backtrace+0xe0/0x130)
[] (nmi_trigger_cpumask_backtrace) from [] (rcu_dump_cpu_stacks+0x9c/0xd8)
[] (rcu_dump_cpu_stacks) from [] (rcu_sched_clock_irq+0x940/0xbec)
[] (rcu_sched_clock_irq) from [] (update_process_times+0x2c/0x54)
[] (update_process_times) from [] (tick_sched_timer+0x5c/0xc0)
[] (tick_sched_timer) from [] (__hrtimer_run_queues+0x140/0x548)
[] (__hrtimer_run_queues) from [] (hrtimer_interrupt+0x134/0x2bc)
[] (hrtimer_interrupt) from [] (arch_timer_handler_phys+0x2c/0x34)
[] (arch_timer_handler_phys) from [] (handle_percpu_devid_irq+0xd4/0x384)
[] (handle_percpu_devid_irq) from [] (generic_handle_irq+0x20/0x34)
[] (generic_handle_irq) from [] (__handle_domain_irq+0x64/0xe0)
[] (__handle_domain_irq) from [] (gic_handle_irq+0x4c/0xa0)
[] (gic_handle_irq) from [] (__irq_svc+0x70/0x98)
Exception stack(0xd8cedd00 to 0xd8cedd48)
dd00: 00000001 d88a5d20 00000000 200a0013 00000000 00000000 c1b3f6f0 0000002a
dd20: d8cec000 00000000 c1b3dbf8 c1b3d6f8 c16c82bc d8cedd50 c018fe50 c019dd68
dd40: 200a0013 ffffffff
[] (__irq_svc) from [] (console_unlock+0x4e0/0x634)
[] (console_unlock) from [] (vprintk_emit+0xf4/0x2d0)
[] (vprintk_emit) from [] (vprintk_default+0x24/0x2c)
[] (vprintk_default) from [] (printk+0x2c/0x54)
[] (printk) from [] (enable_nonboot_cpus+0x38/0x2cc)
[] (enable_nonboot_cpus) from [] (suspend_devices_and_enter+0x374/0xa44)
[] (suspend_devices_and_enter) from [] (pm_suspend+0x2ec/0x3d0)
[] (pm_suspend) from [] (state_store+0x68/0xc8)
[] (state_store) from [] (kernfs_fop_write+0xfc/0x1e0)
[] (kernfs_fop_write) from [] (__vfs_write+0x2c/0x1d0)
[] (__vfs_write) from [] (vfs_write+0xa0/0x180)
[] (vfs_write) from [] (ksys_write+0x5c/0xd8)
[] (ksys_write) from [] (ret_fast_syscall+0x0/0x28)
Exception stack(0xd8cedfa8 to 0xd8cedff0)
dfa0: 00036294 00021590 00000004 bef5cd29 00000007 00000000
dfc0: 00036294 00021590 b6fc0d20 00000004 00000000 00000000 b6fc2fa4 00000000
dfe0: 00000004 bef5c8e8 b6f35d4f b6ec1d16
CPU1 is up
imx6q-pcie 33800000.pcie: Phy link never came up
imx6q-pcie 33800000.pcie: pcie link is down after resume.
mmc1: queuing unknown CIS tuple 0x80 (2 bytes)
mmc1: queuing unknown CIS tuple 0x80 (7 bytes)
mmc1: queuing unknown CIS tuple 0x80 (6 bytes)
PM: resume devices took 0.220 seconds
OOM killer enabled.
Restarting tasks ... done.
PM: suspend exitSigned-off-by: Anson Huang
Reviewed-by: Jacky Bai -
add csi mux setting for imx6qdl
Signed-off-by: Robby Cai
(cherry picked from commit 2e10c8c02446f4fd20ac98172e86b185892480ba) -
The GPC power domain driver add GENPD_FLAG_RPM_ALWAYS_ON to
the i.MX6QP's PU power domain flag, that means it is always ON
for runtime PM but can be OFF during suspend, so no need to
explicitly power ON/OFF PU power for i.MX6QP during suspend/resume
to avoid below dump:Unable to handle kernel NULL pointer dereference at virtual address 00000044
pgd = 20824a30
[00000044] *pgd=4e36d831
Internal error: Oops: 17 [#1] SMP ARM
Modules linked in:
CPU: 0 PID: 732 Comm: sh Tainted: G W 5.3.0-rc3-next-20190809-01770-g0a0b3ec-dir3
Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
PC is at regmap_update_bits_base+0x10/0x74
LR is at imx6_pm_domain_power_on+0xbc/0x1b4
pc : [] lr : [] psr: 600001d3
sp : e9339d68 ip : e9338000 fp : c1a24158
r10: c1308b08 r9 : 00000260 r8 : c1308b08
r7 : c1426120 r6 : c1426120 r5 : c1373580 r4 : 00000000
r3 : 00000001 r2 : 00000001 r1 : 00000260 r0 : 00000000
Flags: nZCv IRQs off FIQs off Mode SVC_32 ISA ARM Segment none
Control: 10c5387d Table: 3949404a DAC: 00000051
Process sh (pid: 732, stack limit = 0x8ba716d6)Signed-off-by: Anson Huang
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Correct i.MX7D debug uart path for Mega/Fast mix off suspend
to avoid output mess during resume.Signed-off-by: Anson Huang
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Add enet MAC address read from efuse.
Signed-off-by: Fugang Duan
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Init ENET RGMII tx clock source, set GPR5[9] to select clock from
internal PLL_enet. And set phy VDDIO to 1.8V that get better signal
quality.Signed-off-by: Fugang Duan
(cherry picked from commit: d7a171fcf5218166f558428610ca8e9cb9f7e830)
Signed-off-by: Arulpandiyan Vadivel -
Disable ethernet phy AR8031 EEE mode in default to reduce the IEEE1588
latency.Signed-off-by: Fugang Duan
Signed-off-by: Arulpandiyan Vadivel -
Correct the clock string "enet_ref" to "enet_clk_ref".
Signed-off-by: Fugang Duan
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The management data input/output (MDIO) bus where often high-speed,
open-drain operation is required. i.MX7D TO1.0 ENET MDIO pin has no
open drain as IC ticket number: TKT252980, i.MX7D TO1.1 fix the issue.Signed-off-by: Fugang Duan
(cherry picked from commit: a747abd5f01d278b91d1b6ee6628e1935cb7b23c)Conflicts:
arch/arm/mach-imx/mach-imx7d.c
Signed-off-by: Arulpandiyan Vadivel -
Enet get MAC address order:
From module parameters or kernel command line -> device tree ->
pfuse -> mac registers set by bootloader -> random mac address.When there have no "fec.macaddr" parameters set in kernel command
line, enet driver get MAC address from device tree. And then if
the MAC address set in device tree and is valid, enet driver get
MAC address from device tree. Otherwise,enet get MAarch/arm/mach-imx
/mach-imx6q.c address from
pfuse. So, in the condition, update the MAC address (read from pfuse)
to device tree.Cherry-pick & Merge patches from:
149ac988a25b8d8eb86d05679cbb7b42819ff7a1 &
3269e5c06bdb2f7ab9bd5afa9bbfe46d872197d3Signed-off-by: Fugang Duan
Signed-off-by: Arulpandiyan Vadivel -
Add i.MX7ULP suspend/resume support, including standby mode
and mem mode, mapped to VLPS and VLLS mode.Signed-off-by: Anson Huang
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Add heartbeat driver for i.mx7ulp.
Signed-off-by: Robin Gong
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Because that the mailbox MU driver is used in i.MX RPMSG implementation.
There is a confliction between this MU driver and the mailbox MU driver.To back-compaible with LPM of iMX6SX, iMX7D and iMX7ULP.
Rename the compatible node of this MU driver.Signed-off-by: Richard Zhu
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Enable the RPMSG for iMX AMP SOC.
Signed-off-by: Richard Zhu
