17 Oct, 2019

1 commit


21 May, 2019

1 commit


16 May, 2019

1 commit

  • Now that we've gotten rid of clk_readl() we can remove io.h from the
    clk-provider header and push out the io.h include to any code that isn't
    already including the io.h header but using things like readl/writel,
    etc.

    Found with this grep:

    git grep -l clk-provider.h | grep '.c$' | xargs git grep -L 'linux/io.h' | \
    xargs git grep -l \
    -e '\' --or \
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    I also reordered a couple includes when they weren't alphabetical and
    removed clk.h from kona, replacing it with clk-provider.h because
    that driver doesn't use clk consumer APIs.

    Acked-by: Geert Uytterhoeven
    Cc: Chen-Yu Tsai
    Acked-by: Maxime Ripard
    Acked-by: Tero Kristo
    Acked-by: Sekhar Nori
    Cc: Krzysztof Kozlowski
    Acked-by: Mark Brown
    Cc: Chris Zankel
    Acked-by: Max Filippov
    Acked-by: John Crispin
    Acked-by: Heiko Stuebner
    Signed-off-by: Stephen Boyd

    Stephen Boyd
     

31 Aug, 2018

1 commit

  • In preparation to remove the node name pointer from struct device_node,
    convert printf users to use the %pOFn format specifier.

    Cc: Eugeniy Paltsev
    Cc: Michael Turquette
    Cc: Stephen Boyd
    Cc: linux-clk@vger.kernel.org
    Cc: linux-arm-kernel@lists.infradead.org
    Cc: linux-renesas-soc@vger.kernel.org
    Cc: linux-omap@vger.kernel.org
    Signed-off-by: Rob Herring
    Signed-off-by: Stephen Boyd

    Rob Herring
     

18 Jul, 2017

1 commit

  • AXS10X boards manages it's clocks using various PLLs. These PLL has same
    dividers and corresponding control registers mapped to different addresses.
    So we add one common driver for such PLLs.

    Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV and
    ODIV. Output clock value is managed using these dividers.

    We add pre-defined tables with supported rate values and appropriate
    configurations of IDIV, FBDIV and ODIV for each value.

    As of today we add support for PLLs that generate clock for the
    following devices:
    * ARC core on AXC CPU tiles.
    * ARC PGU on ARC SDP Mainboard.
    and more to come later.

    By this patch we add support for two plls (arc core pll and pgu pll),
    so we had to use two different init types: CLK_OF_DECLARE for arc core pll and
    regular probing for pgu pll.

    Acked-by: Rob Herring
    Acked-by: Jose Abreu
    Signed-off-by: Eugeniy Paltsev
    Signed-off-by: Vlad Zakharov
    Signed-off-by: Jose Abreu
    [sboyd@codeaurora.org: Silence dubious !x & y sparse warning,
    make of_axs10x_pll_clk_setup() unregister clk on failure]
    Signed-off-by: Stephen Boyd

    Eugeniy Paltsev
     

10 Jan, 2017

1 commit

  • Init field must be cleared in driver probe as this structure is not
    dinamically allocated. If not, wrong flags can be passed to core.

    Signed-off-by: Jose Abreu
    Cc: Carlos Palminha
    Cc: Stephen Boyd
    Cc: Michael Turquette
    Cc: linux-clk@vger.kernel.org
    Cc: linux-kernel@vger.kernel.org
    Fixes: 923587aafc2c ("clk/axs10x: Add I2S PLL clock driver")
    Signed-off-by: Michael Turquette
    Link: lkml.kernel.org/r/040cc9afdfa0e95ce7a01c406ff427ef7dc0c0fd.1481540717.git.joabreu@synopsys.com

    Jose Abreu
     

07 May, 2016

1 commit

  • The ARC SDP I2S clock can be programmed using a
    specific PLL.

    This patch has the goal of adding a clock driver
    that programs this PLL.

    At this moment the rate values are hardcoded in
    a table but in the future it would be ideal to
    use a function which determines the PLL values
    given the desired rate.

    Signed-off-by: Jose Abreu
    Acked-by: Rob Herring
    Signed-off-by: Stephen Boyd

    Jose Abreu