31 May, 2019
1 commit
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Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms and conditions of the gnu general public license
version 2 as published by the free software foundation this program
is distributed in the hope it will be useful but without any
warranty without even the implied warranty of merchantability or
fitness for a particular purpose see the gnu general public license
for more details you should have received a copy of the gnu general
public license along with this program if not see http www gnu org
licensesextracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 228 file(s).
Signed-off-by: Thomas Gleixner
Reviewed-by: Allison Randal
Reviewed-by: Steve Winslow
Reviewed-by: Richard Fontana
Reviewed-by: Alexios Zavras
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de
Signed-off-by: Greg Kroah-Hartman
26 Apr, 2019
1 commit
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STM32F769 clocks are derived from STM32746 clocks.
main differences are:
- new source clock for SAI1 and SAI2 (HSI or HSE)
- Add DFSDM & DSI clocksSigned-off-by: Gabriel Fernandez
Signed-off-by: Stephen Boyd
31 Aug, 2018
1 commit
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In preparation to remove the node name pointer from struct device_node,
convert printf users to use the %pOFn format specifier.Cc: Eugeniy Paltsev
Cc: Michael Turquette
Cc: Stephen Boyd
Cc: linux-clk@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-renesas-soc@vger.kernel.org
Cc: linux-omap@vger.kernel.org
Signed-off-by: Rob Herring
Signed-off-by: Stephen Boyd
20 Mar, 2018
2 commits
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STM32F769 has 2 SDMMC port, add clock entry for the second one.
Signed-off-by: Alexandre TORGUE
Signed-off-by: Patrice Chotard
Signed-off-by: Stephen Boyd -
This patch adds DSI clock for STM32F469 board
Signed-off-by: Gabriel Fernandez
Reviewed-by: Rob Herring
Signed-off-by: Stephen Boyd
07 Dec, 2017
1 commit
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pr_err() messages should end with a new-line to avoid other messages
being concatenated.Signed-off-by: Arvind Yadav
Signed-off-by: Stephen Boyd
22 Jul, 2017
1 commit
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Now that we have a custom printf format specifier, convert users of
full_name to use %pOF instead. This is preparation to remove storing
of the full path string for each node.Signed-off-by: Rob Herring
Cc: Michael Turquette
Cc: Stephen Boyd
Cc: Maxime Coquelin
Cc: Alexandre Torgue
Cc: Russell King
Cc: Matthias Brugger
Cc: Geert Uytterhoeven
Cc: Maxime Ripard
Cc: Chen-Yu Tsai
Cc: "Emilio López"
Cc: Peter De Schrijver
Cc: Prashant Gaikwad
Cc: Thierry Reding
Cc: Jonathan Hunter
Cc: Tero Kristo
Cc: linux-clk@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-mediatek@lists.infradead.org
Cc: linux-renesas-soc@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Cc: linux-omap@vger.kernel.org
Acked-by: Maxime Ripard
Reviewed-by: Geert Uytterhoeven
Acked-by: Geert Uytterhoeven
Acked-by: James Liao
Acked-by: Alexandre TORGUE
Reviewed-by: Matthias Brugger
Signed-off-by: Stephen Boyd
13 Apr, 2017
2 commits
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Use a classic polling to test bit ready.
And the shift of the bit ready of LSE & LSI were wrongs.Fixes: 861adc44d290 ("clk: stm32f4: Add LSI & LSE clocks")
Signed-off-by: Gabriel Fernandez
Signed-off-by: Stephen Boyd
Signed-off-by: Michael Turquette -
0000: PLLQ = 0, wrong configuration
0001: PLLQ = 1, wrong configuration
...
0010: PLLQ = 2
0011: PLLQ = 3
0100: PLLQ = 4
...
1111: PLLQ = 1Use divider table to exclude 0 and 1 values.
Fixes: 83135ad3c517 ("clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards")
Signed-off-by: Gabriel Fernandez
Signed-off-by: Stephen Boyd
Signed-off-by: Michael Turquette
27 Jan, 2017
1 commit
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This patch enables clocks for STM32F746 boards.
Signed-off-by: Gabriel Fernandez
Signed-off-by: Stephen Boyd
13 Jan, 2017
1 commit
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The failure path in the newly added function tries to free an
uninitialized pointer:drivers/clk/clk-stm32f4.c: In function 'stm32f4_rcc_init':
drivers/clk/clk-stm32f4.c:1106:4: error: 'gate' may be used uninitialized in this function [-Werror=maybe-uninitialized]I'm adding an initialization to NULL here to make the kfree()
succeed, and I'm also rearranging the cleanup so that the
same kfree() is used for any error path, making the function
slightly more robust against newly introduced bugs in the
error handling.Fixes: daf2d117cbca ("clk: stm32f4: Add lcd-tft clock")
Signed-off-by: Arnd Bergmann
Acked-by: Gabriel Fernandez
Signed-off-by: Stephen Boyd
10 Jan, 2017
1 commit
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* clk-qcom-rpm8974:
clk: qcom: smd-rpmcc: Add msm8974 clocks* clk-stm32f4:
clk: stm32f4: SDIO & 48Mhz clock management for STM32F469 board
clk: stm32f4: Add SAI clocks
clk: stm32f4: Add I2S clock
clk: stm32f4: Add lcd-tft clock
clk: stm32f4: Add post divisor for I2S & SAI PLLs
clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards
clk: stm32f4: Update DT bindings documentation* clk-ipq4019:
clk: qcom: ipq4019: Add the cpu clock frequency change notifier
clk: qcom: ipq4019: Add all the frequencies for apss cpu
clk: qcom: ipq4019: correct sdcc frequency and parent name
clk: qcom: ipq4019: Add the nodes for pcnoc
clk: qcom: ipq4019: Add the apss cpu pll divider clock node
clk: qcom: ipq4019: remove fixed clocks and add pll clocks* clk-fixes:
clk: stm32f4: Use CLK_OF_DECLARE_DRIVER initialization method
clk: renesas: mstp: Support 8-bit registers for r7s72100
22 Dec, 2016
7 commits
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Clock and reset controller use same compatible strings (same IP).
Since commit 989eafd0b609 ("clk: core: Avoid double initialization of
clocks") the OF core flags clock controllers registered with the
CLK_OF_DECLARE() macro as OF_POPULATED, so platform devices with the same
compatible string will not be registered.Signed-off-by: Gabriel Fernandez
Signed-off-by: Stephen Boyd -
In the stm32f469 soc, the 48Mhz clock could be derived from pll-q or
from pll-sai-p.The SDIO clock could be also derived from 48Mhz or from sys clock.
Signed-off-by: Gabriel Fernandez
Signed-off-by: Stephen Boyd -
This patch introduces SAI clocks for stm32f4 socs.
Signed-off-by: Gabriel Fernandez
Signed-off-by: Stephen Boyd -
This patch introduces I2S clock for stm32f4 soc.
The I2S clock could be derived from an external clock or from pll-i2sSigned-off-by: Gabriel Fernandez
Signed-off-by: Stephen Boyd -
This patch introduces lcd-tft clock for stm32f4 soc.
Signed-off-by: Gabriel Fernandez
Signed-off-by: Stephen Boyd -
This patch adds post dividers of I2S & SAI PLLs.
These dividers are managed by a dedicated register (RCC_DCKCFGR).
The PLL should be off before a set rate.Signed-off-by: Gabriel Fernandez
Signed-off-by: Stephen Boyd -
This patch introduces PLL_I2S and PLL_SAI.
Vco clock of these PLLs can be modify by DT (only n multiplicator,
m divider is still fixed by the boot-loader).
Each PLL has 3 dividers. PLL should be off when we modify the rate.Signed-off-by: Gabriel Fernandez
Acked-by: Rob Herring
[sboyd@codeaurora.org: Mark stm32f4_pll_div_ops static]
Signed-off-by: Stephen Boyd
28 Oct, 2016
3 commits
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This patch adds the QSPI clock for stm32f469 discovery board.
The gate mapping is a little bit different from stm32f429 soc.Signed-off-by: Gabriel Fernandez
Acked-by: Rob Herring
Signed-off-by: Stephen Boyd -
This patch introduces the support of the RTC clock.
RTC clock can have 3 sources: lsi, lse and hse_rtc.Signed-off-by: Gabriel Fernandez
Signed-off-by: Stephen Boyd -
This patch introduces the support of the LSI & LSE clocks.
The clock drivers needs to disable the power domain write protection
using syscon/regmap to enable these clocks.Signed-off-by: Gabriel Fernandez
Signed-off-by: Stephen Boyd
07 Jul, 2016
1 commit
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This is likely that checking 'clks[idx]' instead of 'clks[n]' is
expected here.Signed-off-by: Christophe JAILLET
Signed-off-by: Michael Turquette
Link: lkml.kernel.org/r/1467526003-13318-1-git-send-email-christophe.jaillet@wanadoo.fr
01 Jul, 2016
1 commit
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Now that we have clk_hw based provider APIs to register clks, we
can get rid of struct clk pointers while registering clks in
these drivers, allowing us to move closer to a clear split of
consumer and provider clk APIs.Cc: Daniel Thompson
Signed-off-by: Stephen Boyd
Signed-off-by: Stephen Boyd
25 Aug, 2015
2 commits
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We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.Cc: Daniel Thompson
Signed-off-by: Stephen Boyd -
Mostly converted with the following snippet:
@@
struct clk_hw *E;
@@-__clk_get_flags(E->clk)
+clk_hw_get_flags(E)Acked-by: Tero Kristo
Cc: Maxime Ripard
Cc: Max Filippov
Acked-by: Sebastian Hesselbarth
Cc: Daniel Thompson
Cc: Coquelin
Signed-off-by: Stephen Boyd
03 Jul, 2015
1 commit
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If stm32f4_rcc_lookup() is called with primary == 0 and secondary == 192
then it will read beyond the end of the table array due to an out-by-one
error in the range check.In addition to the fixing the inequality we also modify the r.h.s. to
make it even more explicit that we are comparing against the size of
table in bits.Reported-by: Dan Carpenter
Signed-off-by: Daniel Thompson
Acked-by: Maxime Coquelin
Fixes: 358bdf892f6b ("clk: stm32: Add clock driver for STM32F4[23]xxx devices")
Signed-off-by: Stephen Boyd
23 Jun, 2015
1 commit
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The driver supports decoding and statically modelling PLL state (i.e.
we inherit state from bootloader) and provides support for all
peripherals that support simple one-bit gated clocks. The covers all
peripherals whose clocks come from the AHB, APB1 or APB2 buses.It has been tested on an STM32F429I-Discovery board. The clock counts
for TIM2, USART1 and SYSTICK are all set correctly and the wall clock
looks OK when checked with a stopwatch. I have also tested a prototype
driver for the RNG hardware. The RNG clock is correctly enabled by the
framework (also did inverse test and proved that by changing DT to
configure the wrong clock bit then we observe the RNG driver to fail).Signed-off-by: Daniel Thompson
Reviewed-by: Maxime Coquelin
[sboyd@codeaurora.org: Silence sparse warnings]
Signed-off-by: Stephen Boyd